Discussion:
[PATCH 1/1] PRM: Fixed comments on global PRM register usage.
(too old to reply)
Kalle Jokiniemi
2008-05-06 07:33:01 UTC
Permalink
Signed-off-by: Kalle Jokiniemi <ext-***@nokia.com>
---
arch/arm/mach-omap2/prm.h | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 125d1e2..6715d6f 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -33,7 +33,7 @@

/*
* Architecture-specific global PRM registers
- * Use prm_{read,write}_reg() with these registers.
+ * Use __raw_{read,write}l() with these registers.
*
* With a few exceptions, these are the register names beginning with
* PRCM_* on 24xx, and PRM_* on 34xx. (The exceptions are the
--
1.5.4.3

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Hiroshi DOYU
2008-05-06 10:42:41 UTC
Permalink
"3c18ddd160d1fcd46d1131d9ad6c594dd8e9af99" removed "->nopage()" from "vm_ops".

Signed-off-by: Hiroshi DOYU <***@nokia.com>
---
drivers/dsp/dspgateway/task.c | 7 +++----
1 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/dsp/dspgateway/task.c b/drivers/dsp/dspgateway/task.c
index e5ee8e0..e3a0a02 100644
--- a/drivers/dsp/dspgateway/task.c
+++ b/drivers/dsp/dspgateway/task.c
@@ -1311,16 +1311,15 @@ static void dsp_task_mmap_close(struct vm_area_struct *vma)
* On demand page allocation is not allowed. The mapping area is defined by
* corresponding DSP tasks.
*/
-static struct page *dsp_task_mmap_nopage(struct vm_area_struct *vma,
- unsigned long address, int *type)
+static int dsp_task_mmap_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
{
- return NOPAGE_SIGBUS;
+ return VM_FAULT_NOPAGE;
}

static struct vm_operations_struct dsp_task_vm_ops = {
.open = dsp_task_mmap_open,
.close = dsp_task_mmap_close,
- .nopage = dsp_task_mmap_nopage,
+ .fault = dsp_task_mmap_fault,
};

static int dsp_task_mmap(struct file *filp, struct vm_area_struct *vma)
--
1.5.4.3

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Tony Lindgren
2008-05-06 22:13:46 UTC
Permalink
* Hiroshi DOYU <***@nokia.com> [080506 03:43]:
> "3c18ddd160d1fcd46d1131d9ad6c594dd8e9af99" removed "->nopage()" from "vm_ops".
>
> Signed-off-by: Hiroshi DOYU <***@nokia.com>
> ---
> drivers/dsp/dspgateway/task.c | 7 +++----
> 1 files changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/dsp/dspgateway/task.c b/drivers/dsp/dspgateway/task.c
> index e5ee8e0..e3a0a02 100644
> --- a/drivers/dsp/dspgateway/task.c
> +++ b/drivers/dsp/dspgateway/task.c
> @@ -1311,16 +1311,15 @@ static void dsp_task_mmap_close(struct vm_area_struct *vma)
> * On demand page allocation is not allowed. The mapping area is defined by
> * corresponding DSP tasks.
> */
> -static struct page *dsp_task_mmap_nopage(struct vm_area_struct *vma,
> - unsigned long address, int *type)
> +static int dsp_task_mmap_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
> {
> - return NOPAGE_SIGBUS;
> + return VM_FAULT_NOPAGE;
> }
>
> static struct vm_operations_struct dsp_task_vm_ops = {
> .open = dsp_task_mmap_open,
> .close = dsp_task_mmap_close,
> - .nopage = dsp_task_mmap_nopage,
> + .fault = dsp_task_mmap_fault,
> };
>
> static int dsp_task_mmap(struct file *filp, struct vm_area_struct *vma)

Pushing.

Tony
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Tony Lindgren
2008-05-06 22:13:11 UTC
Permalink
* Kalle Jokiniemi <ext-***@nokia.com> [080506 00:33]:
> Signed-off-by: Kalle Jokiniemi <ext-***@nokia.com>
> ---
> arch/arm/mach-omap2/prm.h | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
> index 125d1e2..6715d6f 100644
> --- a/arch/arm/mach-omap2/prm.h
> +++ b/arch/arm/mach-omap2/prm.h
> @@ -33,7 +33,7 @@
>
> /*
> * Architecture-specific global PRM registers
> - * Use prm_{read,write}_reg() with these registers.
> + * Use __raw_{read,write}l() with these registers.
> *
> * With a few exceptions, these are the register names beginning with
> * PRCM_* on 24xx, and PRM_* on 34xx. (The exceptions are the

Thanks, pushing.

Tony
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Tero Kristo
2008-05-29 14:55:47 UTC
Permalink
This hack will most importantly allow serial console usage when dynamic
idle is enabled.

Note! Functionality under 24xx configuration has not been verified!
There may be some problems with CONFIG_PM_DEBUG flag enabled,
most likely during the PM debug information dumps after / before
sleep. Without this debugging flag this patch should not affect 24xx
devices. Todo: Someone to check functionality under 24xx
configuration and to enable functionality by default on that
platform also.


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Tero Kristo
2008-05-29 14:55:48 UTC
Permalink
UART usage (e.g. serial console) now denies sleep for 5 seconds. This
makes it possible to use serial console when dynamic idle is enabled.

Also moved code from pm-debug.c to serial.c, and made pm24xx.c use this
new implementation.

Signed-off-by: Tero Kristo <***@nokia.com>
---
arch/arm/mach-omap2/pm-debug.c | 132 ------------------------------------
arch/arm/mach-omap2/pm.h | 8 --
arch/arm/mach-omap2/pm24xx.c | 53 ++++++++++-----
arch/arm/mach-omap2/pm34xx.c | 8 ++-
arch/arm/mach-omap2/serial.c | 118 ++++++++++++++++++++++++++++++++
include/asm-arm/arch-omap/common.h | 3 +
6 files changed, 163 insertions(+), 159 deletions(-)

diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 8a9f3c4..c20fa3b 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -34,138 +34,6 @@
#ifdef CONFIG_PM_DEBUG
int omap2_pm_debug = 0;

-static int serial_console_clock_disabled;
-static int serial_console_uart;
-static unsigned int serial_console_next_disable;
-
-static struct clk *console_iclk, *console_fclk;
-
-static void serial_console_kick(void)
-{
- serial_console_next_disable = omap2_read_32k_sync_counter();
- /* Keep the clocks on for 4 secs */
- serial_console_next_disable += 4 * 32768;
-}
-
-static void serial_wait_tx(void)
-{
- static const unsigned long uart_bases[3] = {
- 0x4806a000, 0x4806c000, 0x4806e000
- };
- unsigned long lsr_reg;
- int looped = 0;
-
- /* Wait for TX FIFO and THR to get empty */
- lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart - 1] + (5 << 2));
- while ((__raw_readb(lsr_reg) & 0x60) != 0x60)
- looped = 1;
- if (looped)
- serial_console_kick();
-}
-
-u32 omap2_read_32k_sync_counter(void)
-{
- return omap_readl(OMAP2_32KSYNCT_BASE + 0x0010);
-}
-
-void serial_console_fclk_mask(u32 *f1, u32 *f2)
-{
- switch (serial_console_uart) {
- case 1:
- *f1 &= ~(1 << 21);
- break;
- case 2:
- *f1 &= ~(1 << 22);
- break;
- case 3:
- *f2 &= ~(1 << 2);
- break;
- }
-}
-
-void serial_console_sleep(int enable)
-{
- if (console_iclk == NULL || console_fclk == NULL)
- return;
-
- if (enable) {
- BUG_ON(serial_console_clock_disabled);
- if (clk_get_usecount(console_fclk) == 0)
- return;
- if ((int) serial_console_next_disable - (int) omap2_read_32k_sync_counter() >= 0)
- return;
- serial_wait_tx();
- clk_disable(console_iclk);
- clk_disable(console_fclk);
- serial_console_clock_disabled = 1;
- } else {
- int serial_wakeup = 0;
- u32 l;
-
- switch (serial_console_uart) {
- case 1:
- l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
- if (l & OMAP24XX_ST_UART1)
- serial_wakeup = 1;
- break;
- case 2:
- l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
- if (l & OMAP24XX_ST_UART2)
- serial_wakeup = 1;
- break;
- case 3:
- l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKST2);
- if (l & OMAP24XX_ST_UART3)
- serial_wakeup = 1;
- break;
- }
- if (serial_wakeup)
- serial_console_kick();
- if (!serial_console_clock_disabled)
- return;
- clk_enable(console_iclk);
- clk_enable(console_fclk);
- serial_console_clock_disabled = 0;
- }
-}
-
-void pm_init_serial_console(void)
-{
- const struct omap_serial_console_config *conf;
- char name[16];
-
- conf = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
- struct omap_serial_console_config);
- if (conf == NULL)
- return;
- if (conf->console_uart > 3 || conf->console_uart < 1)
- return;
- serial_console_uart = conf->console_uart;
- sprintf(name, "uart%d_fck", conf->console_uart);
- console_fclk = clk_get(NULL, name);
- if (IS_ERR(console_fclk))
- console_fclk = NULL;
- name[6] = 'i';
- console_iclk = clk_get(NULL, name);
- if (IS_ERR(console_fclk))
- console_iclk = NULL;
- if (console_fclk == NULL || console_iclk == NULL) {
- serial_console_uart = 0;
- return;
- }
- switch (serial_console_uart) {
- case 1:
- prm_set_mod_reg_bits(OMAP24XX_ST_UART1, CORE_MOD, PM_WKEN1);
- break;
- case 2:
- prm_set_mod_reg_bits(OMAP24XX_ST_UART2, CORE_MOD, PM_WKEN1);
- break;
- case 3:
- prm_set_mod_reg_bits(OMAP24XX_ST_UART3, CORE_MOD, OMAP24XX_PM_WKEN2);
- break;
- }
-}
-
#define DUMP_PRM_MOD_REG(mod, reg) \
regs[reg_count].name = #mod "." #reg; \
regs[reg_count++].val = prm_read_mod_reg(mod, reg)
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 351456e..a1a35ea 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -20,18 +20,10 @@ extern unsigned short enable_dyn_sleep;
extern atomic_t sleep_block;

#ifdef CONFIG_PM_DEBUG
-extern u32 omap2_read_32k_sync_counter(void);
extern void omap2_pm_dump(int mode, int resume, unsigned int us);
-extern void serial_console_fclk_mask(u32 *f1, u32 *f2);
-extern void pm_init_serial_console(void);
-extern void serial_console_sleep(int enable);
extern int omap2_pm_debug;
#else
-#define omap2_read_32k_sync_counter() 0;
-#define serial_console_sleep(enable) do; while(0)
-#define pm_init_serial_console() do; while(0)
#define omap2_pm_dump(mode,resume,us) do; while(0)
-#define serial_console_fclk_mask(f1,f2) do; while(0)
#define omap2_pm_debug 0
#endif /* CONFIG_PM_DEBUG */
#endif
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 5d060de..9bb7ae4 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -44,6 +44,7 @@
#include <asm/arch/mux.h>
#include <asm/arch/dma.h>
#include <asm/arch/board.h>
+#include <asm/arch/common.h>

#include "prm.h"
#include "prm-regbits-24xx.h"
@@ -77,7 +78,9 @@ static int omap2_fclks_active(void)

f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
- serial_console_fclk_mask(&f1, &f2);
+#ifdef CONFIG_PM_DEBUG
+ omap_serial_fclk_mask(&f1, &f2);
+#endif
if (f1 | f2)
return 1;
return 0;
@@ -85,7 +88,8 @@ static int omap2_fclks_active(void)

static void omap2_enter_full_retention(void)
{
- u32 l, sleep_time = 0;
+ u32 l = 0;
+ s64 sleep_time = 0;

/* There is 1 reference hold for all children of the oscillator
* clock, the following will remove it. If no one else uses the
@@ -114,29 +118,38 @@ static void omap2_enter_full_retention(void)
omap2_gpio_prepare_for_retention();

if (omap2_pm_debug) {
+ struct timespec t;
omap2_pm_dump(0, 0, 0);
- sleep_time = omap2_read_32k_sync_counter();
+ getnstimeofday(&t);
+ sleep_time = timespec_to_ns(&t);
}

+#ifdef CONFIG_PM_DEBUG
+ omap_serial_enable_clocks(0);
+#endif
+
/* One last check for pending IRQs to avoid extra latency due
* to sleeping unnecessarily. */
if (omap_irq_pending())
goto no_sleep;

- serial_console_sleep(1);
/* Jump to SRAM suspend code */
omap2_sram_suspend(OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
no_sleep:
- serial_console_sleep(0);
+#ifdef CONFIG_PM_DEBUG
+ omap_serial_check_wakeup();
+ omap_serial_enable_clocks(1);
+#endif

if (omap2_pm_debug) {
unsigned long long tmp;
- u32 resume_time;
+ s64 resume_time;
+ struct timespec t;

- resume_time = omap2_read_32k_sync_counter();
+ getnstimeofday(&t);
+ resume_time = timespec_to_ns(&t);
tmp = resume_time - sleep_time;
- tmp *= 1000000;
- omap2_pm_dump(0, 1, tmp / 32768);
+ omap2_pm_dump(0, 1, tmp / 1000);
}
omap2_gpio_resume_after_retention();

@@ -195,7 +208,7 @@ static int omap2_allow_mpu_retention(void)

static void omap2_enter_mpu_retention(void)
{
- u32 sleep_time = 0;
+ s64 sleep_time = 0;
int only_idle = 0;

/* Putting MPU into the WFI state while a transfer is active
@@ -223,20 +236,24 @@ static void omap2_enter_mpu_retention(void)
}

if (omap2_pm_debug) {
+ struct timespec t;
+
omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
- sleep_time = omap2_read_32k_sync_counter();
+ getnstimeofday(&t);
+ sleep_time = timespec_to_ns(&t);
}

omap2_sram_idle();

if (omap2_pm_debug) {
unsigned long long tmp;
- u32 resume_time;
+ s64 resume_time;
+ struct timespec t;

- resume_time = omap2_read_32k_sync_counter();
+ getnstimeofday(&t);
+ resume_time = timespec_to_ns(&t);
tmp = resume_time - sleep_time;
- tmp *= 1000000;
- omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 32768);
+ omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 1000);
}
}

@@ -252,6 +269,10 @@ static int omap2_can_sleep(void)
return 0;
if (omap_dma_running())
return 0;
+#ifdef CONFIG_PM_DEBUG
+ if (!omap_serial_can_sleep())
+ return 0;
+#endif

return 1;
}
@@ -516,8 +537,6 @@ int __init omap2_pm_init(void)

prcm_setup_regs();

- pm_init_serial_console();
-
/* Hack to prevent MPU retention when STI console is enabled. */
{
const struct omap_sti_console_config *sti;
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index abe5cb4..5b68dae 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -94,6 +94,9 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
u32 wkst, irqstatus_mpu;
u32 fclk, iclk;

+ /* Check if we woke up to serial console activity */
+ omap_serial_check_wakeup();
+
/* WKUP */
wkst = prm_read_mod_reg(WKUP_MOD, PM_WKST);
if (wkst) {
@@ -242,8 +245,7 @@ static int omap3_fclks_active(void)
fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
CM_FCLKEN);
gpio_fclk_mask(&fck_per);
- fck_core1 &= ~(0x3 << 13);
- fck_per &= ~(0x1 << 11);
+ omap_serial_fclk_mask(&fck_core1, &fck_per);
if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
fck_cam | fck_per | fck_usbhost)
return 1;
@@ -258,6 +260,8 @@ static int omap3_can_sleep(void)
return 0;
if (atomic_read(&sleep_block) > 0)
return 0;
+ if (!omap_serial_can_sleep())
+ return 0;
return 1;
}

diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index b0fa582..65571f9 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -23,8 +23,47 @@
#include <asm/arch/common.h>
#include <asm/arch/board.h>

+#include "prm.h"
+#include "pm.h"
+
+#define SERIAL_AWAKE_TIME 5
+
static struct clk *uart_ick[OMAP_MAX_NR_PORTS];
static struct clk *uart_fck[OMAP_MAX_NR_PORTS];
+static s64 omap_serial_next_sleep;
+
+static const u32 omap2_uart_wk_st[OMAP_MAX_NR_PORTS] = {
+ PM_WKST1, PM_WKST1, OMAP24XX_PM_WKST2
+};
+static const u32 omap2_uart_wk_en[OMAP_MAX_NR_PORTS] = {
+ PM_WKEN1, PM_WKEN1, OMAP24XX_PM_WKEN2
+};
+const u32 omap2_uart_wk_bit[OMAP_MAX_NR_PORTS] = {
+ OMAP24XX_ST_UART1, OMAP24XX_ST_UART2, OMAP24XX_ST_UART3
+};
+
+#if defined(CONFIG_ARCH_OMAP2)
+static const u32 omap_uart_fclk_mask[OMAP_MAX_NR_PORTS] = {
+ OMAP24XX_EN_UART1, OMAP24XX_EN_UART2, OMAP24XX_EN_UART3
+};
+#endif
+
+#if defined(CONFIG_ARCH_OMAP3)
+static const u32 omap_uart_fclk_mask[OMAP_MAX_NR_PORTS] = {
+ OMAP3430_EN_UART1, OMAP3430_EN_UART2, OMAP3430_EN_UART3
+};
+
+/* UART padconfig registers, these may differ if non-default padconfig
+ is used */
+#define CONTROL_PADCONF_UART1_RX 0x48002182
+#define CONTROL_PADCONF_UART2_RX 0x4800217A
+#define CONTROL_PADCONF_UART3_RX 0x4800219E
+#define PADCONF_WAKEUP_ST 0x8000
+
+static const u32 omap_uart_padconf[OMAP_MAX_NR_PORTS] = {
+ CONTROL_PADCONF_UART1_RX, CONTROL_PADCONF_UART2_RX, CONTROL_PADCONF_UART3_RX
+};
+#endif

static struct plat_serial8250_port serial_platform_data[] = {
{
@@ -83,6 +122,15 @@ static inline void __init omap_serial_reset(struct plat_serial8250_port *p)
serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
}

+static void omap_serial_kick(void)
+{
+ struct timespec t;
+
+ getnstimeofday(&t);
+ omap_serial_next_sleep = timespec_to_ns(&t) +
+ (s64)SERIAL_AWAKE_TIME * (s64)1000000000;
+}
+
void omap_serial_enable_clocks(int enable)
{
int i;
@@ -99,6 +147,71 @@ void omap_serial_enable_clocks(int enable)
}
}

+void omap_serial_fclk_mask(u32 *f1, u32 *f2)
+{
+ if (uart_ick[0])
+ *f1 &= ~omap_uart_fclk_mask[0];
+ if (uart_ick[1])
+ *f1 &= ~omap_uart_fclk_mask[1];
+ if (uart_ick[2])
+ *f2 &= ~omap_uart_fclk_mask[2];
+}
+
+void omap_serial_check_wakeup(void)
+{
+ int i;
+
+ if (cpu_is_omap34xx())
+ for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
+ if (!uart_ick[i])
+ continue;
+ if (omap_readw(omap_uart_padconf[i]) & PADCONF_WAKEUP_ST)
+ omap_serial_kick();
+ return;
+ }
+
+ if (cpu_is_omap24xx()) {
+ u32 l;
+
+ for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
+ if (!uart_ick[i])
+ continue;
+ l = prm_read_mod_reg(CORE_MOD, omap2_uart_wk_st[i]);
+ if (l & omap2_uart_wk_bit[i])
+ omap_serial_kick();
+ return;
+ }
+ }
+}
+
+int omap_serial_can_sleep(void)
+{
+ s64 cnt;
+ int i;
+ struct timespec t;
+
+ struct plat_serial8250_port *p = serial_platform_data;
+
+ getnstimeofday(&t);
+ cnt = timespec_to_ns(&t);
+
+ for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
+ if (!uart_ick[i])
+ continue;
+ /* Check if we have data in the transmit buffer */
+ if ((serial_read_reg(p + i, UART_LSR) & (UART_LSR_TEMT|UART_LSR_THRE))
+ != (UART_LSR_TEMT|UART_LSR_THRE)) {
+ omap_serial_kick();
+ return 0;
+ }
+ }
+
+ if (omap_serial_next_sleep - cnt >= 0)
+ return 0;
+
+ return 1;
+}
+
void __init omap_serial_init(void)
{
int i;
@@ -142,7 +255,12 @@ void __init omap_serial_init(void)
clk_enable(uart_fck[i]);

omap_serial_reset(p);
+
+ if (cpu_is_omap24xx())
+ prm_set_mod_reg_bits(omap2_uart_wk_bit[i], CORE_MOD, omap2_uart_wk_en[i]);
}
+
+ omap_serial_kick();
}

static struct platform_device serial_device = {
diff --git a/include/asm-arm/arch-omap/common.h b/include/asm-arm/arch-omap/common.h
index 6c072de..68894f9 100644
--- a/include/asm-arm/arch-omap/common.h
+++ b/include/asm-arm/arch-omap/common.h
@@ -35,6 +35,9 @@ extern void omap_map_common_io(void);
extern struct sys_timer omap_timer;
extern void omap_serial_init(void);
extern void omap_serial_enable_clocks(int enable);
+extern int omap_serial_can_sleep(void);
+extern void omap_serial_fclk_mask(u32 *f1, u32 *f2);
+void omap_serial_check_wakeup(void);
#ifdef CONFIG_I2C_OMAP
extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
struct i2c_board_info const *info,
--
1.5.4.3

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Tony Lindgren
2008-05-30 23:01:49 UTC
Permalink
Hi,

* Tero Kristo <***@nokia.com> [080529 06:07]:
> UART usage (e.g. serial console) now denies sleep for 5 seconds. This
> makes it possible to use serial console when dynamic idle is enabled.
>
> Also moved code from pm-debug.c to serial.c, and made pm24xx.c use this
> new implementation.

The changes for pm34xx.c don't currently apply, can you please refresh
this patch?

Thanks,

Tony


> Signed-off-by: Tero Kristo <***@nokia.com>
> ---
> arch/arm/mach-omap2/pm-debug.c | 132 ------------------------------------
> arch/arm/mach-omap2/pm.h | 8 --
> arch/arm/mach-omap2/pm24xx.c | 53 ++++++++++-----
> arch/arm/mach-omap2/pm34xx.c | 8 ++-
> arch/arm/mach-omap2/serial.c | 118 ++++++++++++++++++++++++++++++++
> include/asm-arm/arch-omap/common.h | 3 +
> 6 files changed, 163 insertions(+), 159 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
> index 8a9f3c4..c20fa3b 100644
> --- a/arch/arm/mach-omap2/pm-debug.c
> +++ b/arch/arm/mach-omap2/pm-debug.c
> @@ -34,138 +34,6 @@
> #ifdef CONFIG_PM_DEBUG
> int omap2_pm_debug = 0;
>
> -static int serial_console_clock_disabled;
> -static int serial_console_uart;
> -static unsigned int serial_console_next_disable;
> -
> -static struct clk *console_iclk, *console_fclk;
> -
> -static void serial_console_kick(void)
> -{
> - serial_console_next_disable = omap2_read_32k_sync_counter();
> - /* Keep the clocks on for 4 secs */
> - serial_console_next_disable += 4 * 32768;
> -}
> -
> -static void serial_wait_tx(void)
> -{
> - static const unsigned long uart_bases[3] = {
> - 0x4806a000, 0x4806c000, 0x4806e000
> - };
> - unsigned long lsr_reg;
> - int looped = 0;
> -
> - /* Wait for TX FIFO and THR to get empty */
> - lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart - 1] + (5 << 2));
> - while ((__raw_readb(lsr_reg) & 0x60) != 0x60)
> - looped = 1;
> - if (looped)
> - serial_console_kick();
> -}
> -
> -u32 omap2_read_32k_sync_counter(void)
> -{
> - return omap_readl(OMAP2_32KSYNCT_BASE + 0x0010);
> -}
> -
> -void serial_console_fclk_mask(u32 *f1, u32 *f2)
> -{
> - switch (serial_console_uart) {
> - case 1:
> - *f1 &= ~(1 << 21);
> - break;
> - case 2:
> - *f1 &= ~(1 << 22);
> - break;
> - case 3:
> - *f2 &= ~(1 << 2);
> - break;
> - }
> -}
> -
> -void serial_console_sleep(int enable)
> -{
> - if (console_iclk == NULL || console_fclk == NULL)
> - return;
> -
> - if (enable) {
> - BUG_ON(serial_console_clock_disabled);
> - if (clk_get_usecount(console_fclk) == 0)
> - return;
> - if ((int) serial_console_next_disable - (int) omap2_read_32k_sync_counter() >= 0)
> - return;
> - serial_wait_tx();
> - clk_disable(console_iclk);
> - clk_disable(console_fclk);
> - serial_console_clock_disabled = 1;
> - } else {
> - int serial_wakeup = 0;
> - u32 l;
> -
> - switch (serial_console_uart) {
> - case 1:
> - l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
> - if (l & OMAP24XX_ST_UART1)
> - serial_wakeup = 1;
> - break;
> - case 2:
> - l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
> - if (l & OMAP24XX_ST_UART2)
> - serial_wakeup = 1;
> - break;
> - case 3:
> - l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKST2);
> - if (l & OMAP24XX_ST_UART3)
> - serial_wakeup = 1;
> - break;
> - }
> - if (serial_wakeup)
> - serial_console_kick();
> - if (!serial_console_clock_disabled)
> - return;
> - clk_enable(console_iclk);
> - clk_enable(console_fclk);
> - serial_console_clock_disabled = 0;
> - }
> -}
> -
> -void pm_init_serial_console(void)
> -{
> - const struct omap_serial_console_config *conf;
> - char name[16];
> -
> - conf = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
> - struct omap_serial_console_config);
> - if (conf == NULL)
> - return;
> - if (conf->console_uart > 3 || conf->console_uart < 1)
> - return;
> - serial_console_uart = conf->console_uart;
> - sprintf(name, "uart%d_fck", conf->console_uart);
> - console_fclk = clk_get(NULL, name);
> - if (IS_ERR(console_fclk))
> - console_fclk = NULL;
> - name[6] = 'i';
> - console_iclk = clk_get(NULL, name);
> - if (IS_ERR(console_fclk))
> - console_iclk = NULL;
> - if (console_fclk == NULL || console_iclk == NULL) {
> - serial_console_uart = 0;
> - return;
> - }
> - switch (serial_console_uart) {
> - case 1:
> - prm_set_mod_reg_bits(OMAP24XX_ST_UART1, CORE_MOD, PM_WKEN1);
> - break;
> - case 2:
> - prm_set_mod_reg_bits(OMAP24XX_ST_UART2, CORE_MOD, PM_WKEN1);
> - break;
> - case 3:
> - prm_set_mod_reg_bits(OMAP24XX_ST_UART3, CORE_MOD, OMAP24XX_PM_WKEN2);
> - break;
> - }
> -}
> -
> #define DUMP_PRM_MOD_REG(mod, reg) \
> regs[reg_count].name = #mod "." #reg; \
> regs[reg_count++].val = prm_read_mod_reg(mod, reg)
> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
> index 351456e..a1a35ea 100644
> --- a/arch/arm/mach-omap2/pm.h
> +++ b/arch/arm/mach-omap2/pm.h
> @@ -20,18 +20,10 @@ extern unsigned short enable_dyn_sleep;
> extern atomic_t sleep_block;
>
> #ifdef CONFIG_PM_DEBUG
> -extern u32 omap2_read_32k_sync_counter(void);
> extern void omap2_pm_dump(int mode, int resume, unsigned int us);
> -extern void serial_console_fclk_mask(u32 *f1, u32 *f2);
> -extern void pm_init_serial_console(void);
> -extern void serial_console_sleep(int enable);
> extern int omap2_pm_debug;
> #else
> -#define omap2_read_32k_sync_counter() 0;
> -#define serial_console_sleep(enable) do; while(0)
> -#define pm_init_serial_console() do; while(0)
> #define omap2_pm_dump(mode,resume,us) do; while(0)
> -#define serial_console_fclk_mask(f1,f2) do; while(0)
> #define omap2_pm_debug 0
> #endif /* CONFIG_PM_DEBUG */
> #endif
> diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
> index 5d060de..9bb7ae4 100644
> --- a/arch/arm/mach-omap2/pm24xx.c
> +++ b/arch/arm/mach-omap2/pm24xx.c
> @@ -44,6 +44,7 @@
> #include <asm/arch/mux.h>
> #include <asm/arch/dma.h>
> #include <asm/arch/board.h>
> +#include <asm/arch/common.h>
>
> #include "prm.h"
> #include "prm-regbits-24xx.h"
> @@ -77,7 +78,9 @@ static int omap2_fclks_active(void)
>
> f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
> f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
> - serial_console_fclk_mask(&f1, &f2);
> +#ifdef CONFIG_PM_DEBUG
> + omap_serial_fclk_mask(&f1, &f2);
> +#endif
> if (f1 | f2)
> return 1;
> return 0;
> @@ -85,7 +88,8 @@ static int omap2_fclks_active(void)
>
> static void omap2_enter_full_retention(void)
> {
> - u32 l, sleep_time = 0;
> + u32 l = 0;
> + s64 sleep_time = 0;
>
> /* There is 1 reference hold for all children of the oscillator
> * clock, the following will remove it. If no one else uses the
> @@ -114,29 +118,38 @@ static void omap2_enter_full_retention(void)
> omap2_gpio_prepare_for_retention();
>
> if (omap2_pm_debug) {
> + struct timespec t;
> omap2_pm_dump(0, 0, 0);
> - sleep_time = omap2_read_32k_sync_counter();
> + getnstimeofday(&t);
> + sleep_time = timespec_to_ns(&t);
> }
>
> +#ifdef CONFIG_PM_DEBUG
> + omap_serial_enable_clocks(0);
> +#endif
> +
> /* One last check for pending IRQs to avoid extra latency due
> * to sleeping unnecessarily. */
> if (omap_irq_pending())
> goto no_sleep;
>
> - serial_console_sleep(1);
> /* Jump to SRAM suspend code */
> omap2_sram_suspend(OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
> no_sleep:
> - serial_console_sleep(0);
> +#ifdef CONFIG_PM_DEBUG
> + omap_serial_check_wakeup();
> + omap_serial_enable_clocks(1);
> +#endif
>
> if (omap2_pm_debug) {
> unsigned long long tmp;
> - u32 resume_time;
> + s64 resume_time;
> + struct timespec t;
>
> - resume_time = omap2_read_32k_sync_counter();
> + getnstimeofday(&t);
> + resume_time = timespec_to_ns(&t);
> tmp = resume_time - sleep_time;
> - tmp *= 1000000;
> - omap2_pm_dump(0, 1, tmp / 32768);
> + omap2_pm_dump(0, 1, tmp / 1000);
> }
> omap2_gpio_resume_after_retention();
>
> @@ -195,7 +208,7 @@ static int omap2_allow_mpu_retention(void)
>
> static void omap2_enter_mpu_retention(void)
> {
> - u32 sleep_time = 0;
> + s64 sleep_time = 0;
> int only_idle = 0;
>
> /* Putting MPU into the WFI state while a transfer is active
> @@ -223,20 +236,24 @@ static void omap2_enter_mpu_retention(void)
> }
>
> if (omap2_pm_debug) {
> + struct timespec t;
> +
> omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
> - sleep_time = omap2_read_32k_sync_counter();
> + getnstimeofday(&t);
> + sleep_time = timespec_to_ns(&t);
> }
>
> omap2_sram_idle();
>
> if (omap2_pm_debug) {
> unsigned long long tmp;
> - u32 resume_time;
> + s64 resume_time;
> + struct timespec t;
>
> - resume_time = omap2_read_32k_sync_counter();
> + getnstimeofday(&t);
> + resume_time = timespec_to_ns(&t);
> tmp = resume_time - sleep_time;
> - tmp *= 1000000;
> - omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 32768);
> + omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 1000);
> }
> }
>
> @@ -252,6 +269,10 @@ static int omap2_can_sleep(void)
> return 0;
> if (omap_dma_running())
> return 0;
> +#ifdef CONFIG_PM_DEBUG
> + if (!omap_serial_can_sleep())
> + return 0;
> +#endif
>
> return 1;
> }
> @@ -516,8 +537,6 @@ int __init omap2_pm_init(void)
>
> prcm_setup_regs();
>
> - pm_init_serial_console();
> -
> /* Hack to prevent MPU retention when STI console is enabled. */
> {
> const struct omap_sti_console_config *sti;
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index abe5cb4..5b68dae 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -94,6 +94,9 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
> u32 wkst, irqstatus_mpu;
> u32 fclk, iclk;
>
> + /* Check if we woke up to serial console activity */
> + omap_serial_check_wakeup();
> +
> /* WKUP */
> wkst = prm_read_mod_reg(WKUP_MOD, PM_WKST);
> if (wkst) {
> @@ -242,8 +245,7 @@ static int omap3_fclks_active(void)
> fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
> CM_FCLKEN);
> gpio_fclk_mask(&fck_per);
> - fck_core1 &= ~(0x3 << 13);
> - fck_per &= ~(0x1 << 11);
> + omap_serial_fclk_mask(&fck_core1, &fck_per);
> if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
> fck_cam | fck_per | fck_usbhost)
> return 1;
> @@ -258,6 +260,8 @@ static int omap3_can_sleep(void)
> return 0;
> if (atomic_read(&sleep_block) > 0)
> return 0;
> + if (!omap_serial_can_sleep())
> + return 0;
> return 1;
> }
>
> diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
> index b0fa582..65571f9 100644
> --- a/arch/arm/mach-omap2/serial.c
> +++ b/arch/arm/mach-omap2/serial.c
> @@ -23,8 +23,47 @@
> #include <asm/arch/common.h>
> #include <asm/arch/board.h>
>
> +#include "prm.h"
> +#include "pm.h"
> +
> +#define SERIAL_AWAKE_TIME 5
> +
> static struct clk *uart_ick[OMAP_MAX_NR_PORTS];
> static struct clk *uart_fck[OMAP_MAX_NR_PORTS];
> +static s64 omap_serial_next_sleep;
> +
> +static const u32 omap2_uart_wk_st[OMAP_MAX_NR_PORTS] = {
> + PM_WKST1, PM_WKST1, OMAP24XX_PM_WKST2
> +};
> +static const u32 omap2_uart_wk_en[OMAP_MAX_NR_PORTS] = {
> + PM_WKEN1, PM_WKEN1, OMAP24XX_PM_WKEN2
> +};
> +const u32 omap2_uart_wk_bit[OMAP_MAX_NR_PORTS] = {
> + OMAP24XX_ST_UART1, OMAP24XX_ST_UART2, OMAP24XX_ST_UART3
> +};
> +
> +#if defined(CONFIG_ARCH_OMAP2)
> +static const u32 omap_uart_fclk_mask[OMAP_MAX_NR_PORTS] = {
> + OMAP24XX_EN_UART1, OMAP24XX_EN_UART2, OMAP24XX_EN_UART3
> +};
> +#endif
> +
> +#if defined(CONFIG_ARCH_OMAP3)
> +static const u32 omap_uart_fclk_mask[OMAP_MAX_NR_PORTS] = {
> + OMAP3430_EN_UART1, OMAP3430_EN_UART2, OMAP3430_EN_UART3
> +};
> +
> +/* UART padconfig registers, these may differ if non-default padconfig
> + is used */
> +#define CONTROL_PADCONF_UART1_RX 0x48002182
> +#define CONTROL_PADCONF_UART2_RX 0x4800217A
> +#define CONTROL_PADCONF_UART3_RX 0x4800219E
> +#define PADCONF_WAKEUP_ST 0x8000
> +
> +static const u32 omap_uart_padconf[OMAP_MAX_NR_PORTS] = {
> + CONTROL_PADCONF_UART1_RX, CONTROL_PADCONF_UART2_RX, CONTROL_PADCONF_UART3_RX
> +};
> +#endif
>
> static struct plat_serial8250_port serial_platform_data[] = {
> {
> @@ -83,6 +122,15 @@ static inline void __init omap_serial_reset(struct plat_serial8250_port *p)
> serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
> }
>
> +static void omap_serial_kick(void)
> +{
> + struct timespec t;
> +
> + getnstimeofday(&t);
> + omap_serial_next_sleep = timespec_to_ns(&t) +
> + (s64)SERIAL_AWAKE_TIME * (s64)1000000000;
> +}
> +
> void omap_serial_enable_clocks(int enable)
> {
> int i;
> @@ -99,6 +147,71 @@ void omap_serial_enable_clocks(int enable)
> }
> }
>
> +void omap_serial_fclk_mask(u32 *f1, u32 *f2)
> +{
> + if (uart_ick[0])
> + *f1 &= ~omap_uart_fclk_mask[0];
> + if (uart_ick[1])
> + *f1 &= ~omap_uart_fclk_mask[1];
> + if (uart_ick[2])
> + *f2 &= ~omap_uart_fclk_mask[2];
> +}
> +
> +void omap_serial_check_wakeup(void)
> +{
> + int i;
> +
> + if (cpu_is_omap34xx())
> + for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
> + if (!uart_ick[i])
> + continue;
> + if (omap_readw(omap_uart_padconf[i]) & PADCONF_WAKEUP_ST)
> + omap_serial_kick();
> + return;
> + }
> +
> + if (cpu_is_omap24xx()) {
> + u32 l;
> +
> + for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
> + if (!uart_ick[i])
> + continue;
> + l = prm_read_mod_reg(CORE_MOD, omap2_uart_wk_st[i]);
> + if (l & omap2_uart_wk_bit[i])
> + omap_serial_kick();
> + return;
> + }
> + }
> +}
> +
> +int omap_serial_can_sleep(void)
> +{
> + s64 cnt;
> + int i;
> + struct timespec t;
> +
> + struct plat_serial8250_port *p = serial_platform_data;
> +
> + getnstimeofday(&t);
> + cnt = timespec_to_ns(&t);
> +
> + for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
> + if (!uart_ick[i])
> + continue;
> + /* Check if we have data in the transmit buffer */
> + if ((serial_read_reg(p + i, UART_LSR) & (UART_LSR_TEMT|UART_LSR_THRE))
> + != (UART_LSR_TEMT|UART_LSR_THRE)) {
> + omap_serial_kick();
> + return 0;
> + }
> + }
> +
> + if (omap_serial_next_sleep - cnt >= 0)
> + return 0;
> +
> + return 1;
> +}
> +
> void __init omap_serial_init(void)
> {
> int i;
> @@ -142,7 +255,12 @@ void __init omap_serial_init(void)
> clk_enable(uart_fck[i]);
>
> omap_serial_reset(p);
> +
> + if (cpu_is_omap24xx())
> + prm_set_mod_reg_bits(omap2_uart_wk_bit[i], CORE_MOD, omap2_uart_wk_en[i]);
> }
> +
> + omap_serial_kick();
> }
>
> static struct platform_device serial_device = {
> diff --git a/include/asm-arm/arch-omap/common.h b/include/asm-arm/arch-omap/common.h
> index 6c072de..68894f9 100644
> --- a/include/asm-arm/arch-omap/common.h
> +++ b/include/asm-arm/arch-omap/common.h
> @@ -35,6 +35,9 @@ extern void omap_map_common_io(void);
> extern struct sys_timer omap_timer;
> extern void omap_serial_init(void);
> extern void omap_serial_enable_clocks(int enable);
> +extern int omap_serial_can_sleep(void);
> +extern void omap_serial_fclk_mask(u32 *f1, u32 *f2);
> +void omap_serial_check_wakeup(void);
> #ifdef CONFIG_I2C_OMAP
> extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
> struct i2c_board_info const *info,
> --
> 1.5.4.3
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to ***@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
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T***@nokia.com
2008-06-02 08:09:20 UTC
Permalink
Hi,

This patch currently depends on at least one of the PM workaround
patches from Jouni Hogander. Namely this one:

[PATCH 07/10] 34XX: PM: Workaround to check whether any fck is active
before entering sleep

Sorry I think I forgot to mention this in the patch note. Should we
change the patch in order to make this one apply cleanly (I could make a
separate patch for the UART fclk hack which depends on the above?)

-Tero

>-----Original Message-----
>From: ext Tony Lindgren [mailto:***@atomide.com]
>Sent: 31 May, 2008 02:02
>To: Kristo Tero (Nokia-D/Tampere)
>Cc: linux-***@vger.kernel.org
>Subject: Re: [PATCH 1/1] Added sleep support to UART
>
>Hi,
>
>* Tero Kristo <***@nokia.com> [080529 06:07]:
>> UART usage (e.g. serial console) now denies sleep for 5
>seconds. This
>> makes it possible to use serial console when dynamic idle is enabled.
>>
>> Also moved code from pm-debug.c to serial.c, and made pm24xx.c use
>> this new implementation.
>
>The changes for pm34xx.c don't currently apply, can you please
>refresh this patch?
>
>Thanks,
>
>Tony
>
>
>> Signed-off-by: Tero Kristo <***@nokia.com>
>> ---
>> arch/arm/mach-omap2/pm-debug.c | 132
>------------------------------------
>> arch/arm/mach-omap2/pm.h | 8 --
>> arch/arm/mach-omap2/pm24xx.c | 53 ++++++++++-----
>> arch/arm/mach-omap2/pm34xx.c | 8 ++-
>> arch/arm/mach-omap2/serial.c | 118
>++++++++++++++++++++++++++++++++
>> include/asm-arm/arch-omap/common.h | 3 +
>> 6 files changed, 163 insertions(+), 159 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/pm-debug.c
>> b/arch/arm/mach-omap2/pm-debug.c index 8a9f3c4..c20fa3b 100644
>> --- a/arch/arm/mach-omap2/pm-debug.c
>> +++ b/arch/arm/mach-omap2/pm-debug.c
>> @@ -34,138 +34,6 @@
>> #ifdef CONFIG_PM_DEBUG
>> int omap2_pm_debug = 0;
>>
>> -static int serial_console_clock_disabled; -static int
>> serial_console_uart; -static unsigned int
>serial_console_next_disable;
>> -
>> -static struct clk *console_iclk, *console_fclk;
>> -
>> -static void serial_console_kick(void) -{
>> - serial_console_next_disable = omap2_read_32k_sync_counter();
>> - /* Keep the clocks on for 4 secs */
>> - serial_console_next_disable += 4 * 32768;
>> -}
>> -
>> -static void serial_wait_tx(void)
>> -{
>> - static const unsigned long uart_bases[3] = {
>> - 0x4806a000, 0x4806c000, 0x4806e000
>> - };
>> - unsigned long lsr_reg;
>> - int looped = 0;
>> -
>> - /* Wait for TX FIFO and THR to get empty */
>> - lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart -
>1] + (5 << 2));
>> - while ((__raw_readb(lsr_reg) & 0x60) != 0x60)
>> - looped = 1;
>> - if (looped)
>> - serial_console_kick();
>> -}
>> -
>> -u32 omap2_read_32k_sync_counter(void) -{
>> - return omap_readl(OMAP2_32KSYNCT_BASE + 0x0010);
>> -}
>> -
>> -void serial_console_fclk_mask(u32 *f1, u32 *f2) -{
>> - switch (serial_console_uart) {
>> - case 1:
>> - *f1 &= ~(1 << 21);
>> - break;
>> - case 2:
>> - *f1 &= ~(1 << 22);
>> - break;
>> - case 3:
>> - *f2 &= ~(1 << 2);
>> - break;
>> - }
>> -}
>> -
>> -void serial_console_sleep(int enable) -{
>> - if (console_iclk == NULL || console_fclk == NULL)
>> - return;
>> -
>> - if (enable) {
>> - BUG_ON(serial_console_clock_disabled);
>> - if (clk_get_usecount(console_fclk) == 0)
>> - return;
>> - if ((int) serial_console_next_disable - (int)
>omap2_read_32k_sync_counter() >= 0)
>> - return;
>> - serial_wait_tx();
>> - clk_disable(console_iclk);
>> - clk_disable(console_fclk);
>> - serial_console_clock_disabled = 1;
>> - } else {
>> - int serial_wakeup = 0;
>> - u32 l;
>> -
>> - switch (serial_console_uart) {
>> - case 1:
>> - l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
>> - if (l & OMAP24XX_ST_UART1)
>> - serial_wakeup = 1;
>> - break;
>> - case 2:
>> - l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
>> - if (l & OMAP24XX_ST_UART2)
>> - serial_wakeup = 1;
>> - break;
>> - case 3:
>> - l = prm_read_mod_reg(CORE_MOD,
>OMAP24XX_PM_WKST2);
>> - if (l & OMAP24XX_ST_UART3)
>> - serial_wakeup = 1;
>> - break;
>> - }
>> - if (serial_wakeup)
>> - serial_console_kick();
>> - if (!serial_console_clock_disabled)
>> - return;
>> - clk_enable(console_iclk);
>> - clk_enable(console_fclk);
>> - serial_console_clock_disabled = 0;
>> - }
>> -}
>> -
>> -void pm_init_serial_console(void)
>> -{
>> - const struct omap_serial_console_config *conf;
>> - char name[16];
>> -
>> - conf = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
>> - struct omap_serial_console_config);
>> - if (conf == NULL)
>> - return;
>> - if (conf->console_uart > 3 || conf->console_uart < 1)
>> - return;
>> - serial_console_uart = conf->console_uart;
>> - sprintf(name, "uart%d_fck", conf->console_uart);
>> - console_fclk = clk_get(NULL, name);
>> - if (IS_ERR(console_fclk))
>> - console_fclk = NULL;
>> - name[6] = 'i';
>> - console_iclk = clk_get(NULL, name);
>> - if (IS_ERR(console_fclk))
>> - console_iclk = NULL;
>> - if (console_fclk == NULL || console_iclk == NULL) {
>> - serial_console_uart = 0;
>> - return;
>> - }
>> - switch (serial_console_uart) {
>> - case 1:
>> - prm_set_mod_reg_bits(OMAP24XX_ST_UART1,
>CORE_MOD, PM_WKEN1);
>> - break;
>> - case 2:
>> - prm_set_mod_reg_bits(OMAP24XX_ST_UART2,
>CORE_MOD, PM_WKEN1);
>> - break;
>> - case 3:
>> - prm_set_mod_reg_bits(OMAP24XX_ST_UART3,
>CORE_MOD, OMAP24XX_PM_WKEN2);
>> - break;
>> - }
>> -}
>> -
>> #define DUMP_PRM_MOD_REG(mod, reg) \
>> regs[reg_count].name = #mod "." #reg; \
>> regs[reg_count++].val = prm_read_mod_reg(mod, reg) diff --git
>> a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index
>> 351456e..a1a35ea 100644
>> --- a/arch/arm/mach-omap2/pm.h
>> +++ b/arch/arm/mach-omap2/pm.h
>> @@ -20,18 +20,10 @@ extern unsigned short enable_dyn_sleep; extern
>> atomic_t sleep_block;
>>
>> #ifdef CONFIG_PM_DEBUG
>> -extern u32 omap2_read_32k_sync_counter(void);
>> extern void omap2_pm_dump(int mode, int resume, unsigned int us);
>> -extern void serial_console_fclk_mask(u32 *f1, u32 *f2);
>-extern void
>> pm_init_serial_console(void); -extern void serial_console_sleep(int
>> enable); extern int omap2_pm_debug; #else -#define
>> omap2_read_32k_sync_counter() 0; -#define
>serial_console_sleep(enable)
>> do; while(0) -#define pm_init_serial_console() do; while(0) #define
>> omap2_pm_dump(mode,resume,us) do; while(0) -#define
>> serial_console_fclk_mask(f1,f2) do; while(0) #define
>omap2_pm_debug
>> 0 #endif /* CONFIG_PM_DEBUG */ #endif diff --git
>> a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index
>> 5d060de..9bb7ae4 100644
>> --- a/arch/arm/mach-omap2/pm24xx.c
>> +++ b/arch/arm/mach-omap2/pm24xx.c
>> @@ -44,6 +44,7 @@
>> #include <asm/arch/mux.h>
>> #include <asm/arch/dma.h>
>> #include <asm/arch/board.h>
>> +#include <asm/arch/common.h>
>>
>> #include "prm.h"
>> #include "prm-regbits-24xx.h"
>> @@ -77,7 +78,9 @@ static int omap2_fclks_active(void)
>>
>> f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
>> f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
>> - serial_console_fclk_mask(&f1, &f2);
>> +#ifdef CONFIG_PM_DEBUG
>> + omap_serial_fclk_mask(&f1, &f2);
>> +#endif
>> if (f1 | f2)
>> return 1;
>> return 0;
>> @@ -85,7 +88,8 @@ static int omap2_fclks_active(void)
>>
>> static void omap2_enter_full_retention(void) {
>> - u32 l, sleep_time = 0;
>> + u32 l = 0;
>> + s64 sleep_time = 0;
>>
>> /* There is 1 reference hold for all children of the oscillator
>> * clock, the following will remove it. If no one else
>uses the @@
>> -114,29 +118,38 @@ static void omap2_enter_full_retention(void)
>> omap2_gpio_prepare_for_retention();
>>
>> if (omap2_pm_debug) {
>> + struct timespec t;
>> omap2_pm_dump(0, 0, 0);
>> - sleep_time = omap2_read_32k_sync_counter();
>> + getnstimeofday(&t);
>> + sleep_time = timespec_to_ns(&t);
>> }
>>
>> +#ifdef CONFIG_PM_DEBUG
>> + omap_serial_enable_clocks(0);
>> +#endif
>> +
>> /* One last check for pending IRQs to avoid extra latency due
>> * to sleeping unnecessarily. */
>> if (omap_irq_pending())
>> goto no_sleep;
>>
>> - serial_console_sleep(1);
>> /* Jump to SRAM suspend code */
>> omap2_sram_suspend(OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
>> no_sleep:
>> - serial_console_sleep(0);
>> +#ifdef CONFIG_PM_DEBUG
>> + omap_serial_check_wakeup();
>> + omap_serial_enable_clocks(1);
>> +#endif
>>
>> if (omap2_pm_debug) {
>> unsigned long long tmp;
>> - u32 resume_time;
>> + s64 resume_time;
>> + struct timespec t;
>>
>> - resume_time = omap2_read_32k_sync_counter();
>> + getnstimeofday(&t);
>> + resume_time = timespec_to_ns(&t);
>> tmp = resume_time - sleep_time;
>> - tmp *= 1000000;
>> - omap2_pm_dump(0, 1, tmp / 32768);
>> + omap2_pm_dump(0, 1, tmp / 1000);
>> }
>> omap2_gpio_resume_after_retention();
>>
>> @@ -195,7 +208,7 @@ static int omap2_allow_mpu_retention(void)
>>
>> static void omap2_enter_mpu_retention(void) {
>> - u32 sleep_time = 0;
>> + s64 sleep_time = 0;
>> int only_idle = 0;
>>
>> /* Putting MPU into the WFI state while a transfer is active @@
>> -223,20 +236,24 @@ static void omap2_enter_mpu_retention(void)
>> }
>>
>> if (omap2_pm_debug) {
>> + struct timespec t;
>> +
>> omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
>> - sleep_time = omap2_read_32k_sync_counter();
>> + getnstimeofday(&t);
>> + sleep_time = timespec_to_ns(&t);
>> }
>>
>> omap2_sram_idle();
>>
>> if (omap2_pm_debug) {
>> unsigned long long tmp;
>> - u32 resume_time;
>> + s64 resume_time;
>> + struct timespec t;
>>
>> - resume_time = omap2_read_32k_sync_counter();
>> + getnstimeofday(&t);
>> + resume_time = timespec_to_ns(&t);
>> tmp = resume_time - sleep_time;
>> - tmp *= 1000000;
>> - omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 32768);
>> + omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 1000);
>> }
>> }
>>
>> @@ -252,6 +269,10 @@ static int omap2_can_sleep(void)
>> return 0;
>> if (omap_dma_running())
>> return 0;
>> +#ifdef CONFIG_PM_DEBUG
>> + if (!omap_serial_can_sleep())
>> + return 0;
>> +#endif
>>
>> return 1;
>> }
>> @@ -516,8 +537,6 @@ int __init omap2_pm_init(void)
>>
>> prcm_setup_regs();
>>
>> - pm_init_serial_console();
>> -
>> /* Hack to prevent MPU retention when STI console is enabled. */
>> {
>> const struct omap_sti_console_config *sti; diff --git
>> a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index
>> abe5cb4..5b68dae 100644
>> --- a/arch/arm/mach-omap2/pm34xx.c
>> +++ b/arch/arm/mach-omap2/pm34xx.c
>> @@ -94,6 +94,9 @@ static irqreturn_t prcm_interrupt_handler
>(int irq, void *dev_id)
>> u32 wkst, irqstatus_mpu;
>> u32 fclk, iclk;
>>
>> + /* Check if we woke up to serial console activity */
>> + omap_serial_check_wakeup();
>> +
>> /* WKUP */
>> wkst = prm_read_mod_reg(WKUP_MOD, PM_WKST);
>> if (wkst) {
>> @@ -242,8 +245,7 @@ static int omap3_fclks_active(void)
>> fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
>> CM_FCLKEN);
>> gpio_fclk_mask(&fck_per);
>> - fck_core1 &= ~(0x3 << 13);
>> - fck_per &= ~(0x1 << 11);
>> + omap_serial_fclk_mask(&fck_core1, &fck_per);
>> if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
>> fck_cam | fck_per | fck_usbhost)
>> return 1;
>> @@ -258,6 +260,8 @@ static int omap3_can_sleep(void)
>> return 0;
>> if (atomic_read(&sleep_block) > 0)
>> return 0;
>> + if (!omap_serial_can_sleep())
>> + return 0;
>> return 1;
>> }
>>
>> diff --git a/arch/arm/mach-omap2/serial.c
>> b/arch/arm/mach-omap2/serial.c index b0fa582..65571f9 100644
>> --- a/arch/arm/mach-omap2/serial.c
>> +++ b/arch/arm/mach-omap2/serial.c
>> @@ -23,8 +23,47 @@
>> #include <asm/arch/common.h>
>> #include <asm/arch/board.h>
>>
>> +#include "prm.h"
>> +#include "pm.h"
>> +
>> +#define SERIAL_AWAKE_TIME 5
>> +
>> static struct clk *uart_ick[OMAP_MAX_NR_PORTS]; static struct clk
>> *uart_fck[OMAP_MAX_NR_PORTS];
>> +static s64 omap_serial_next_sleep;
>> +
>> +static const u32 omap2_uart_wk_st[OMAP_MAX_NR_PORTS] = {
>> + PM_WKST1, PM_WKST1, OMAP24XX_PM_WKST2 }; static const u32
>> +omap2_uart_wk_en[OMAP_MAX_NR_PORTS] = {
>> + PM_WKEN1, PM_WKEN1, OMAP24XX_PM_WKEN2 }; const u32
>> +omap2_uart_wk_bit[OMAP_MAX_NR_PORTS] = {
>> + OMAP24XX_ST_UART1, OMAP24XX_ST_UART2, OMAP24XX_ST_UART3 };
>> +
>> +#if defined(CONFIG_ARCH_OMAP2)
>> +static const u32 omap_uart_fclk_mask[OMAP_MAX_NR_PORTS] = {
>> + OMAP24XX_EN_UART1, OMAP24XX_EN_UART2, OMAP24XX_EN_UART3
>}; #endif
>> +
>> +#if defined(CONFIG_ARCH_OMAP3)
>> +static const u32 omap_uart_fclk_mask[OMAP_MAX_NR_PORTS] = {
>> + OMAP3430_EN_UART1, OMAP3430_EN_UART2, OMAP3430_EN_UART3 };
>> +
>> +/* UART padconfig registers, these may differ if
>non-default padconfig
>> + is used */
>> +#define CONTROL_PADCONF_UART1_RX 0x48002182 #define
>> +CONTROL_PADCONF_UART2_RX 0x4800217A #define
>CONTROL_PADCONF_UART3_RX
>> +0x4800219E #define PADCONF_WAKEUP_ST 0x8000
>> +
>> +static const u32 omap_uart_padconf[OMAP_MAX_NR_PORTS] = {
>> + CONTROL_PADCONF_UART1_RX, CONTROL_PADCONF_UART2_RX,
>> +CONTROL_PADCONF_UART3_RX }; #endif
>>
>> static struct plat_serial8250_port serial_platform_data[] = {
>> {
>> @@ -83,6 +122,15 @@ static inline void __init
>omap_serial_reset(struct plat_serial8250_port *p)
>> serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 <<
>2) | (1 <<
>> 0)); }
>>
>> +static void omap_serial_kick(void)
>> +{
>> + struct timespec t;
>> +
>> + getnstimeofday(&t);
>> + omap_serial_next_sleep = timespec_to_ns(&t) +
>> + (s64)SERIAL_AWAKE_TIME * (s64)1000000000; }
>> +
>> void omap_serial_enable_clocks(int enable) {
>> int i;
>> @@ -99,6 +147,71 @@ void omap_serial_enable_clocks(int enable)
>> }
>> }
>>
>> +void omap_serial_fclk_mask(u32 *f1, u32 *f2) {
>> + if (uart_ick[0])
>> + *f1 &= ~omap_uart_fclk_mask[0];
>> + if (uart_ick[1])
>> + *f1 &= ~omap_uart_fclk_mask[1];
>> + if (uart_ick[2])
>> + *f2 &= ~omap_uart_fclk_mask[2];
>> +}
>> +
>> +void omap_serial_check_wakeup(void)
>> +{
>> + int i;
>> +
>> + if (cpu_is_omap34xx())
>> + for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
>> + if (!uart_ick[i])
>> + continue;
>> + if (omap_readw(omap_uart_padconf[i]) &
>PADCONF_WAKEUP_ST)
>> + omap_serial_kick();
>> + return;
>> + }
>> +
>> + if (cpu_is_omap24xx()) {
>> + u32 l;
>> +
>> + for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
>> + if (!uart_ick[i])
>> + continue;
>> + l = prm_read_mod_reg(CORE_MOD,
>omap2_uart_wk_st[i]);
>> + if (l & omap2_uart_wk_bit[i])
>> + omap_serial_kick();
>> + return;
>> + }
>> + }
>> +}
>> +
>> +int omap_serial_can_sleep(void)
>> +{
>> + s64 cnt;
>> + int i;
>> + struct timespec t;
>> +
>> + struct plat_serial8250_port *p = serial_platform_data;
>> +
>> + getnstimeofday(&t);
>> + cnt = timespec_to_ns(&t);
>> +
>> + for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
>> + if (!uart_ick[i])
>> + continue;
>> + /* Check if we have data in the transmit buffer */
>> + if ((serial_read_reg(p + i, UART_LSR) &
>(UART_LSR_TEMT|UART_LSR_THRE))
>> + != (UART_LSR_TEMT|UART_LSR_THRE)) {
>> + omap_serial_kick();
>> + return 0;
>> + }
>> + }
>> +
>> + if (omap_serial_next_sleep - cnt >= 0)
>> + return 0;
>> +
>> + return 1;
>> +}
>> +
>> void __init omap_serial_init(void)
>> {
>> int i;
>> @@ -142,7 +255,12 @@ void __init omap_serial_init(void)
>> clk_enable(uart_fck[i]);
>>
>> omap_serial_reset(p);
>> +
>> + if (cpu_is_omap24xx())
>> +
>prm_set_mod_reg_bits(omap2_uart_wk_bit[i], CORE_MOD,
>> +omap2_uart_wk_en[i]);
>> }
>> +
>> + omap_serial_kick();
>> }
>>
>> static struct platform_device serial_device = { diff --git
>> a/include/asm-arm/arch-omap/common.h
>> b/include/asm-arm/arch-omap/common.h
>> index 6c072de..68894f9 100644
>> --- a/include/asm-arm/arch-omap/common.h
>> +++ b/include/asm-arm/arch-omap/common.h
>> @@ -35,6 +35,9 @@ extern void omap_map_common_io(void);
>extern struct
>> sys_timer omap_timer; extern void omap_serial_init(void); extern
>> void omap_serial_enable_clocks(int enable);
>> +extern int omap_serial_can_sleep(void); extern void
>> +omap_serial_fclk_mask(u32 *f1, u32 *f2); void
>> +omap_serial_check_wakeup(void);
>> #ifdef CONFIG_I2C_OMAP
>> extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
>> struct i2c_board_info const *info,
>> --
>> 1.5.4.3
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe
>linux-omap"
>> in the body of a message to ***@vger.kernel.org More majordomo
>> info at http://vger.kernel.org/majordomo-info.html
>
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Tony Lindgren
2008-06-02 16:29:07 UTC
Permalink
* ***@nokia.com <***@nokia.com> [080602 01:09]:
> Hi,
>
> This patch currently depends on at least one of the PM workaround
> patches from Jouni Hogander. Namely this one:
>
> [PATCH 07/10] 34XX: PM: Workaround to check whether any fck is active
> before entering sleep
>
> Sorry I think I forgot to mention this in the patch note. Should we
> change the patch in order to make this one apply cleanly (I could make a
> separate patch for the UART fclk hack which depends on the above?)

Yeah that would be great.

Tony


>
> -Tero
>
> >-----Original Message-----
> >From: ext Tony Lindgren [mailto:***@atomide.com]
> >Sent: 31 May, 2008 02:02
> >To: Kristo Tero (Nokia-D/Tampere)
> >Cc: linux-***@vger.kernel.org
> >Subject: Re: [PATCH 1/1] Added sleep support to UART
> >
> >Hi,
> >
> >* Tero Kristo <***@nokia.com> [080529 06:07]:
> >> UART usage (e.g. serial console) now denies sleep for 5
> >seconds. This
> >> makes it possible to use serial console when dynamic idle is enabled.
> >>
> >> Also moved code from pm-debug.c to serial.c, and made pm24xx.c use
> >> this new implementation.
> >
> >The changes for pm34xx.c don't currently apply, can you please
> >refresh this patch?
> >
> >Thanks,
> >
> >Tony
> >
> >
> >> Signed-off-by: Tero Kristo <***@nokia.com>
> >> ---
> >> arch/arm/mach-omap2/pm-debug.c | 132
> >------------------------------------
> >> arch/arm/mach-omap2/pm.h | 8 --
> >> arch/arm/mach-omap2/pm24xx.c | 53 ++++++++++-----
> >> arch/arm/mach-omap2/pm34xx.c | 8 ++-
> >> arch/arm/mach-omap2/serial.c | 118
> >++++++++++++++++++++++++++++++++
> >> include/asm-arm/arch-omap/common.h | 3 +
> >> 6 files changed, 163 insertions(+), 159 deletions(-)
> >>
> >> diff --git a/arch/arm/mach-omap2/pm-debug.c
> >> b/arch/arm/mach-omap2/pm-debug.c index 8a9f3c4..c20fa3b 100644
> >> --- a/arch/arm/mach-omap2/pm-debug.c
> >> +++ b/arch/arm/mach-omap2/pm-debug.c
> >> @@ -34,138 +34,6 @@
> >> #ifdef CONFIG_PM_DEBUG
> >> int omap2_pm_debug = 0;
> >>
> >> -static int serial_console_clock_disabled; -static int
> >> serial_console_uart; -static unsigned int
> >serial_console_next_disable;
> >> -
> >> -static struct clk *console_iclk, *console_fclk;
> >> -
> >> -static void serial_console_kick(void) -{
> >> - serial_console_next_disable = omap2_read_32k_sync_counter();
> >> - /* Keep the clocks on for 4 secs */
> >> - serial_console_next_disable += 4 * 32768;
> >> -}
> >> -
> >> -static void serial_wait_tx(void)
> >> -{
> >> - static const unsigned long uart_bases[3] = {
> >> - 0x4806a000, 0x4806c000, 0x4806e000
> >> - };
> >> - unsigned long lsr_reg;
> >> - int looped = 0;
> >> -
> >> - /* Wait for TX FIFO and THR to get empty */
> >> - lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart -
> >1] + (5 << 2));
> >> - while ((__raw_readb(lsr_reg) & 0x60) != 0x60)
> >> - looped = 1;
> >> - if (looped)
> >> - serial_console_kick();
> >> -}
> >> -
> >> -u32 omap2_read_32k_sync_counter(void) -{
> >> - return omap_readl(OMAP2_32KSYNCT_BASE + 0x0010);
> >> -}
> >> -
> >> -void serial_console_fclk_mask(u32 *f1, u32 *f2) -{
> >> - switch (serial_console_uart) {
> >> - case 1:
> >> - *f1 &= ~(1 << 21);
> >> - break;
> >> - case 2:
> >> - *f1 &= ~(1 << 22);
> >> - break;
> >> - case 3:
> >> - *f2 &= ~(1 << 2);
> >> - break;
> >> - }
> >> -}
> >> -
> >> -void serial_console_sleep(int enable) -{
> >> - if (console_iclk == NULL || console_fclk == NULL)
> >> - return;
> >> -
> >> - if (enable) {
> >> - BUG_ON(serial_console_clock_disabled);
> >> - if (clk_get_usecount(console_fclk) == 0)
> >> - return;
> >> - if ((int) serial_console_next_disable - (int)
> >omap2_read_32k_sync_counter() >= 0)
> >> - return;
> >> - serial_wait_tx();
> >> - clk_disable(console_iclk);
> >> - clk_disable(console_fclk);
> >> - serial_console_clock_disabled = 1;
> >> - } else {
> >> - int serial_wakeup = 0;
> >> - u32 l;
> >> -
> >> - switch (serial_console_uart) {
> >> - case 1:
> >> - l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
> >> - if (l & OMAP24XX_ST_UART1)
> >> - serial_wakeup = 1;
> >> - break;
> >> - case 2:
> >> - l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
> >> - if (l & OMAP24XX_ST_UART2)
> >> - serial_wakeup = 1;
> >> - break;
> >> - case 3:
> >> - l = prm_read_mod_reg(CORE_MOD,
> >OMAP24XX_PM_WKST2);
> >> - if (l & OMAP24XX_ST_UART3)
> >> - serial_wakeup = 1;
> >> - break;
> >> - }
> >> - if (serial_wakeup)
> >> - serial_console_kick();
> >> - if (!serial_console_clock_disabled)
> >> - return;
> >> - clk_enable(console_iclk);
> >> - clk_enable(console_fclk);
> >> - serial_console_clock_disabled = 0;
> >> - }
> >> -}
> >> -
> >> -void pm_init_serial_console(void)
> >> -{
> >> - const struct omap_serial_console_config *conf;
> >> - char name[16];
> >> -
> >> - conf = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
> >> - struct omap_serial_console_config);
> >> - if (conf == NULL)
> >> - return;
> >> - if (conf->console_uart > 3 || conf->console_uart < 1)
> >> - return;
> >> - serial_console_uart = conf->console_uart;
> >> - sprintf(name, "uart%d_fck", conf->console_uart);
> >> - console_fclk = clk_get(NULL, name);
> >> - if (IS_ERR(console_fclk))
> >> - console_fclk = NULL;
> >> - name[6] = 'i';
> >> - console_iclk = clk_get(NULL, name);
> >> - if (IS_ERR(console_fclk))
> >> - console_iclk = NULL;
> >> - if (console_fclk == NULL || console_iclk == NULL) {
> >> - serial_console_uart = 0;
> >> - return;
> >> - }
> >> - switch (serial_console_uart) {
> >> - case 1:
> >> - prm_set_mod_reg_bits(OMAP24XX_ST_UART1,
> >CORE_MOD, PM_WKEN1);
> >> - break;
> >> - case 2:
> >> - prm_set_mod_reg_bits(OMAP24XX_ST_UART2,
> >CORE_MOD, PM_WKEN1);
> >> - break;
> >> - case 3:
> >> - prm_set_mod_reg_bits(OMAP24XX_ST_UART3,
> >CORE_MOD, OMAP24XX_PM_WKEN2);
> >> - break;
> >> - }
> >> -}
> >> -
> >> #define DUMP_PRM_MOD_REG(mod, reg) \
> >> regs[reg_count].name = #mod "." #reg; \
> >> regs[reg_count++].val = prm_read_mod_reg(mod, reg) diff --git
> >> a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index
> >> 351456e..a1a35ea 100644
> >> --- a/arch/arm/mach-omap2/pm.h
> >> +++ b/arch/arm/mach-omap2/pm.h
> >> @@ -20,18 +20,10 @@ extern unsigned short enable_dyn_sleep; extern
> >> atomic_t sleep_block;
> >>
> >> #ifdef CONFIG_PM_DEBUG
> >> -extern u32 omap2_read_32k_sync_counter(void);
> >> extern void omap2_pm_dump(int mode, int resume, unsigned int us);
> >> -extern void serial_console_fclk_mask(u32 *f1, u32 *f2);
> >-extern void
> >> pm_init_serial_console(void); -extern void serial_console_sleep(int
> >> enable); extern int omap2_pm_debug; #else -#define
> >> omap2_read_32k_sync_counter() 0; -#define
> >serial_console_sleep(enable)
> >> do; while(0) -#define pm_init_serial_console() do; while(0) #define
> >> omap2_pm_dump(mode,resume,us) do; while(0) -#define
> >> serial_console_fclk_mask(f1,f2) do; while(0) #define
> >omap2_pm_debug
> >> 0 #endif /* CONFIG_PM_DEBUG */ #endif diff --git
> >> a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index
> >> 5d060de..9bb7ae4 100644
> >> --- a/arch/arm/mach-omap2/pm24xx.c
> >> +++ b/arch/arm/mach-omap2/pm24xx.c
> >> @@ -44,6 +44,7 @@
> >> #include <asm/arch/mux.h>
> >> #include <asm/arch/dma.h>
> >> #include <asm/arch/board.h>
> >> +#include <asm/arch/common.h>
> >>
> >> #include "prm.h"
> >> #include "prm-regbits-24xx.h"
> >> @@ -77,7 +78,9 @@ static int omap2_fclks_active(void)
> >>
> >> f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
> >> f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
> >> - serial_console_fclk_mask(&f1, &f2);
> >> +#ifdef CONFIG_PM_DEBUG
> >> + omap_serial_fclk_mask(&f1, &f2);
> >> +#endif
> >> if (f1 | f2)
> >> return 1;
> >> return 0;
> >> @@ -85,7 +88,8 @@ static int omap2_fclks_active(void)
> >>
> >> static void omap2_enter_full_retention(void) {
> >> - u32 l, sleep_time = 0;
> >> + u32 l = 0;
> >> + s64 sleep_time = 0;
> >>
> >> /* There is 1 reference hold for all children of the oscillator
> >> * clock, the following will remove it. If no one else
> >uses the @@
> >> -114,29 +118,38 @@ static void omap2_enter_full_retention(void)
> >> omap2_gpio_prepare_for_retention();
> >>
> >> if (omap2_pm_debug) {
> >> + struct timespec t;
> >> omap2_pm_dump(0, 0, 0);
> >> - sleep_time = omap2_read_32k_sync_counter();
> >> + getnstimeofday(&t);
> >> + sleep_time = timespec_to_ns(&t);
> >> }
> >>
> >> +#ifdef CONFIG_PM_DEBUG
> >> + omap_serial_enable_clocks(0);
> >> +#endif
> >> +
> >> /* One last check for pending IRQs to avoid extra latency due
> >> * to sleeping unnecessarily. */
> >> if (omap_irq_pending())
> >> goto no_sleep;
> >>
> >> - serial_console_sleep(1);
> >> /* Jump to SRAM suspend code */
> >> omap2_sram_suspend(OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
> >> no_sleep:
> >> - serial_console_sleep(0);
> >> +#ifdef CONFIG_PM_DEBUG
> >> + omap_serial_check_wakeup();
> >> + omap_serial_enable_clocks(1);
> >> +#endif
> >>
> >> if (omap2_pm_debug) {
> >> unsigned long long tmp;
> >> - u32 resume_time;
> >> + s64 resume_time;
> >> + struct timespec t;
> >>
> >> - resume_time = omap2_read_32k_sync_counter();
> >> + getnstimeofday(&t);
> >> + resume_time = timespec_to_ns(&t);
> >> tmp = resume_time - sleep_time;
> >> - tmp *= 1000000;
> >> - omap2_pm_dump(0, 1, tmp / 32768);
> >> + omap2_pm_dump(0, 1, tmp / 1000);
> >> }
> >> omap2_gpio_resume_after_retention();
> >>
> >> @@ -195,7 +208,7 @@ static int omap2_allow_mpu_retention(void)
> >>
> >> static void omap2_enter_mpu_retention(void) {
> >> - u32 sleep_time = 0;
> >> + s64 sleep_time = 0;
> >> int only_idle = 0;
> >>
> >> /* Putting MPU into the WFI state while a transfer is active @@
> >> -223,20 +236,24 @@ static void omap2_enter_mpu_retention(void)
> >> }
> >>
> >> if (omap2_pm_debug) {
> >> + struct timespec t;
> >> +
> >> omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
> >> - sleep_time = omap2_read_32k_sync_counter();
> >> + getnstimeofday(&t);
> >> + sleep_time = timespec_to_ns(&t);
> >> }
> >>
> >> omap2_sram_idle();
> >>
> >> if (omap2_pm_debug) {
> >> unsigned long long tmp;
> >> - u32 resume_time;
> >> + s64 resume_time;
> >> + struct timespec t;
> >>
> >> - resume_time = omap2_read_32k_sync_counter();
> >> + getnstimeofday(&t);
> >> + resume_time = timespec_to_ns(&t);
> >> tmp = resume_time - sleep_time;
> >> - tmp *= 1000000;
> >> - omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 32768);
> >> + omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 1000);
> >> }
> >> }
> >>
> >> @@ -252,6 +269,10 @@ static int omap2_can_sleep(void)
> >> return 0;
> >> if (omap_dma_running())
> >> return 0;
> >> +#ifdef CONFIG_PM_DEBUG
> >> + if (!omap_serial_can_sleep())
> >> + return 0;
> >> +#endif
> >>
> >> return 1;
> >> }
> >> @@ -516,8 +537,6 @@ int __init omap2_pm_init(void)
> >>
> >> prcm_setup_regs();
> >>
> >> - pm_init_serial_console();
> >> -
> >> /* Hack to prevent MPU retention when STI console is enabled. */
> >> {
> >> const struct omap_sti_console_config *sti; diff --git
> >> a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index
> >> abe5cb4..5b68dae 100644
> >> --- a/arch/arm/mach-omap2/pm34xx.c
> >> +++ b/arch/arm/mach-omap2/pm34xx.c
> >> @@ -94,6 +94,9 @@ static irqreturn_t prcm_interrupt_handler
> >(int irq, void *dev_id)
> >> u32 wkst, irqstatus_mpu;
> >> u32 fclk, iclk;
> >>
> >> + /* Check if we woke up to serial console activity */
> >> + omap_serial_check_wakeup();
> >> +
> >> /* WKUP */
> >> wkst = prm_read_mod_reg(WKUP_MOD, PM_WKST);
> >> if (wkst) {
> >> @@ -242,8 +245,7 @@ static int omap3_fclks_active(void)
> >> fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
> >> CM_FCLKEN);
> >> gpio_fclk_mask(&fck_per);
> >> - fck_core1 &= ~(0x3 << 13);
> >> - fck_per &= ~(0x1 << 11);
> >> + omap_serial_fclk_mask(&fck_core1, &fck_per);
> >> if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
> >> fck_cam | fck_per | fck_usbhost)
> >> return 1;
> >> @@ -258,6 +260,8 @@ static int omap3_can_sleep(void)
> >> return 0;
> >> if (atomic_read(&sleep_block) > 0)
> >> return 0;
> >> + if (!omap_serial_can_sleep())
> >> + return 0;
> >> return 1;
> >> }
> >>
> >> diff --git a/arch/arm/mach-omap2/serial.c
> >> b/arch/arm/mach-omap2/serial.c index b0fa582..65571f9 100644
> >> --- a/arch/arm/mach-omap2/serial.c
> >> +++ b/arch/arm/mach-omap2/serial.c
> >> @@ -23,8 +23,47 @@
> >> #include <asm/arch/common.h>
> >> #include <asm/arch/board.h>
> >>
> >> +#include "prm.h"
> >> +#include "pm.h"
> >> +
> >> +#define SERIAL_AWAKE_TIME 5
> >> +
> >> static struct clk *uart_ick[OMAP_MAX_NR_PORTS]; static struct clk
> >> *uart_fck[OMAP_MAX_NR_PORTS];
> >> +static s64 omap_serial_next_sleep;
> >> +
> >> +static const u32 omap2_uart_wk_st[OMAP_MAX_NR_PORTS] = {
> >> + PM_WKST1, PM_WKST1, OMAP24XX_PM_WKST2 }; static const u32
> >> +omap2_uart_wk_en[OMAP_MAX_NR_PORTS] = {
> >> + PM_WKEN1, PM_WKEN1, OMAP24XX_PM_WKEN2 }; const u32
> >> +omap2_uart_wk_bit[OMAP_MAX_NR_PORTS] = {
> >> + OMAP24XX_ST_UART1, OMAP24XX_ST_UART2, OMAP24XX_ST_UART3 };
> >> +
> >> +#if defined(CONFIG_ARCH_OMAP2)
> >> +static const u32 omap_uart_fclk_mask[OMAP_MAX_NR_PORTS] = {
> >> + OMAP24XX_EN_UART1, OMAP24XX_EN_UART2, OMAP24XX_EN_UART3
> >}; #endif
> >> +
> >> +#if defined(CONFIG_ARCH_OMAP3)
> >> +static const u32 omap_uart_fclk_mask[OMAP_MAX_NR_PORTS] = {
> >> + OMAP3430_EN_UART1, OMAP3430_EN_UART2, OMAP3430_EN_UART3 };
> >> +
> >> +/* UART padconfig registers, these may differ if
> >non-default padconfig
> >> + is used */
> >> +#define CONTROL_PADCONF_UART1_RX 0x48002182 #define
> >> +CONTROL_PADCONF_UART2_RX 0x4800217A #define
> >CONTROL_PADCONF_UART3_RX
> >> +0x4800219E #define PADCONF_WAKEUP_ST 0x8000
> >> +
> >> +static const u32 omap_uart_padconf[OMAP_MAX_NR_PORTS] = {
> >> + CONTROL_PADCONF_UART1_RX, CONTROL_PADCONF_UART2_RX,
> >> +CONTROL_PADCONF_UART3_RX }; #endif
> >>
> >> static struct plat_serial8250_port serial_platform_data[] = {
> >> {
> >> @@ -83,6 +122,15 @@ static inline void __init
> >omap_serial_reset(struct plat_serial8250_port *p)
> >> serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 <<
> >2) | (1 <<
> >> 0)); }
> >>
> >> +static void omap_serial_kick(void)
> >> +{
> >> + struct timespec t;
> >> +
> >> + getnstimeofday(&t);
> >> + omap_serial_next_sleep = timespec_to_ns(&t) +
> >> + (s64)SERIAL_AWAKE_TIME * (s64)1000000000; }
> >> +
> >> void omap_serial_enable_clocks(int enable) {
> >> int i;
> >> @@ -99,6 +147,71 @@ void omap_serial_enable_clocks(int enable)
> >> }
> >> }
> >>
> >> +void omap_serial_fclk_mask(u32 *f1, u32 *f2) {
> >> + if (uart_ick[0])
> >> + *f1 &= ~omap_uart_fclk_mask[0];
> >> + if (uart_ick[1])
> >> + *f1 &= ~omap_uart_fclk_mask[1];
> >> + if (uart_ick[2])
> >> + *f2 &= ~omap_uart_fclk_mask[2];
> >> +}
> >> +
> >> +void omap_serial_check_wakeup(void)
> >> +{
> >> + int i;
> >> +
> >> + if (cpu_is_omap34xx())
> >> + for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
> >> + if (!uart_ick[i])
> >> + continue;
> >> + if (omap_readw(omap_uart_padconf[i]) &
> >PADCONF_WAKEUP_ST)
> >> + omap_serial_kick();
> >> + return;
> >> + }
> >> +
> >> + if (cpu_is_omap24xx()) {
> >> + u32 l;
> >> +
> >> + for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
> >> + if (!uart_ick[i])
> >> + continue;
> >> + l = prm_read_mod_reg(CORE_MOD,
> >omap2_uart_wk_st[i]);
> >> + if (l & omap2_uart_wk_bit[i])
> >> + omap_serial_kick();
> >> + return;
> >> + }
> >> + }
> >> +}
> >> +
> >> +int omap_serial_can_sleep(void)
> >> +{
> >> + s64 cnt;
> >> + int i;
> >> + struct timespec t;
> >> +
> >> + struct plat_serial8250_port *p = serial_platform_data;
> >> +
> >> + getnstimeofday(&t);
> >> + cnt = timespec_to_ns(&t);
> >> +
> >> + for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
> >> + if (!uart_ick[i])
> >> + continue;
> >> + /* Check if we have data in the transmit buffer */
> >> + if ((serial_read_reg(p + i, UART_LSR) &
> >(UART_LSR_TEMT|UART_LSR_THRE))
> >> + != (UART_LSR_TEMT|UART_LSR_THRE)) {
> >> + omap_serial_kick();
> >> + return 0;
> >> + }
> >> + }
> >> +
> >> + if (omap_serial_next_sleep - cnt >= 0)
> >> + return 0;
> >> +
> >> + return 1;
> >> +}
> >> +
> >> void __init omap_serial_init(void)
> >> {
> >> int i;
> >> @@ -142,7 +255,12 @@ void __init omap_serial_init(void)
> >> clk_enable(uart_fck[i]);
> >>
> >> omap_serial_reset(p);
> >> +
> >> + if (cpu_is_omap24xx())
> >> +
> >prm_set_mod_reg_bits(omap2_uart_wk_bit[i], CORE_MOD,
> >> +omap2_uart_wk_en[i]);
> >> }
> >> +
> >> + omap_serial_kick();
> >> }
> >>
> >> static struct platform_device serial_device = { diff --git
> >> a/include/asm-arm/arch-omap/common.h
> >> b/include/asm-arm/arch-omap/common.h
> >> index 6c072de..68894f9 100644
> >> --- a/include/asm-arm/arch-omap/common.h
> >> +++ b/include/asm-arm/arch-omap/common.h
> >> @@ -35,6 +35,9 @@ extern void omap_map_common_io(void);
> >extern struct
> >> sys_timer omap_timer; extern void omap_serial_init(void); extern
> >> void omap_serial_enable_clocks(int enable);
> >> +extern int omap_serial_can_sleep(void); extern void
> >> +omap_serial_fclk_mask(u32 *f1, u32 *f2); void
> >> +omap_serial_check_wakeup(void);
> >> #ifdef CONFIG_I2C_OMAP
> >> extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
> >> struct i2c_board_info const *info,
> >> --
> >> 1.5.4.3
> >>
> >> --
> >> To unsubscribe from this list: send the line "unsubscribe
> >linux-omap"
> >> in the body of a message to ***@vger.kernel.org More majordomo
> >> info at http://vger.kernel.org/majordomo-info.html
> >
--
To unsubscribe from this list: send the line "unsubscribe linux-omap" in
the body of a message to ***@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Kalle Jokiniemi
2008-05-30 14:12:27 UTC
Permalink
- Changed register accesses to use __raw_readl(), __raw_writel() and
prm_rmw_reg_bits() functions instread of "REG_X = REG_Y" type accesses.

- Changed direct register clock enables/disables to clockframework calls.

- replaced cpu-related #ifdefs with if (cpu_is_xxxx()) calls.

- removed EFUSE related ifdefs

- added smartreflex_disable/enable calls to pm34xx.c suspend function.

- Added smartreflex.o into compilation, depends on CONFIG_ARCH_OMAP34XX and
CONFIG_TWL4030_CORE

Signed-off-by: Kalle Jokiniemi <ext-***@nokia.com>
---
arch/arm/mach-omap2/Makefile | 4 +
arch/arm/mach-omap2/pm34xx.c | 9 +
arch/arm/mach-omap2/smartreflex.c | 406 +++++++++++++++++++++----------------
3 files changed, 247 insertions(+), 172 deletions(-)

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index b617b66..6a4c7e7 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -21,6 +21,10 @@ endif
ifeq ($(CONFIG_ARCH_OMAP3),y)
obj-$(CONFIG_PM) += pm34xx.o sleep34xx.o
endif
+
+ifeq ($(CONFIG_ARCH_OMAP34XX),y)
+obj-$(CONFIG_TWL4030_CORE) += smartreflex.o
+endif
obj-$(CONFIG_PM_DEBUG) += pm-debug.o

# Clock framework
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index a1bfb30..fbba2f3 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -36,6 +36,7 @@

#include "prm.h"
#include "pm.h"
+#include "smartreflex.h"

struct power_state {
struct powerdomain *pwrdm;
@@ -243,6 +244,10 @@ static int omap3_pm_suspend(void)
struct power_state *pwrst;
int state, ret = 0;

+ /* XXX Disable smartreflex before entering suspend */
+ disable_smartreflex(SR1);
+ disable_smartreflex(SR2);
+
/* Read current next_pwrsts */
list_for_each_entry(pwrst, &pwrst_list, node)
pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
@@ -274,6 +279,10 @@ restore:
printk(KERN_INFO "Successfully put all powerdomains "
"to target state\n");

+ /* XXX Enable smartreflex after suspend */
+ enable_smartreflex(SR1);
+ enable_smartreflex(SR2);
+
return ret;
}

diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index dae7460..068944c 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -3,6 +3,9 @@
*
* OMAP34XX SmartReflex Voltage Control
*
+ * Copyright (C) 2008 Nokia Corporation
+ * Kalle Jokiniemi
+ *
* Copyright (C) 2007 Texas Instruments, Inc.
* Lesly A M <***@ti.com>
*
@@ -20,13 +23,14 @@
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/sysfs.h>
-
-#include <asm/arch/prcm.h>
-#include <asm/arch/power_companion.h>
+#include <linux/kobject.h>
+#include <linux/i2c/twl4030.h>
#include <linux/io.h>

-#include "prcm-regs.h"
+#include <asm/arch/omap34xx.h>
+
#include "smartreflex.h"
+#include "prm-regbits-34xx.h"


/* #define DEBUG_SR 1 */
@@ -37,11 +41,16 @@
# define DPRINTK(fmt, args...)
#endif

+/* XXX: These should be relocated where-ever the OPP implementation will be */
+u32 current_vdd1_opp;
+u32 current_vdd2_opp;
+
struct omap_sr{
int srid;
int is_sr_reset;
int is_autocomp_active;
struct clk *fck;
+ u32 clk_length;
u32 req_opp_no;
u32 opp1_nvalue, opp2_nvalue, opp3_nvalue, opp4_nvalue, opp5_nvalue;
u32 senp_mod, senn_mod;
@@ -53,6 +62,7 @@ static struct omap_sr sr1 = {
.srid = SR1,
.is_sr_reset = 1,
.is_autocomp_active = 0,
+ .clk_length = 0,
.srbase_addr = OMAP34XX_SR1_BASE,
};

@@ -60,6 +70,7 @@ static struct omap_sr sr2 = {
.srid = SR2,
.is_sr_reset = 1,
.is_autocomp_active = 0,
+ .clk_length = 0,
.srbase_addr = OMAP34XX_SR2_BASE,
};

@@ -85,8 +96,6 @@ static inline u32 sr_read_reg(struct omap_sr *sr, int offset)
return omap_readl(sr->srbase_addr + offset);
}

-
-#ifndef USE_EFUSE_VALUES
static void cal_reciprocal(u32 sensor, u32 *sengain, u32 *rnsen)
{
u32 gn, rn, mul;
@@ -100,7 +109,21 @@ static void cal_reciprocal(u32 sensor, u32 *sengain, u32 *rnsen)
}
}
}
-#endif
+
+static void sr_clk_get(struct omap_sr *sr)
+{
+ if (sr->srid == SR1) {
+ sr->fck = clk_get(NULL, "sr1_fck");
+ if (IS_ERR(sr->fck))
+ printk(KERN_ERR "Could not get sr1_fck\n");
+
+ } else if (sr->srid == SR2) {
+ sr->fck = clk_get(NULL, "sr2_fck");
+ if (IS_ERR(sr->fck))
+ printk(KERN_ERR "Could not get sr2_fck\n");
+
+ }
+}

static int sr_clk_enable(struct omap_sr *sr)
{
@@ -131,20 +154,48 @@ static int sr_clk_disable(struct omap_sr *sr)
return 0;
}

+static void sr_set_clk_length(struct omap_sr *sr)
+{
+ struct clk *osc_sys_ck;
+ u32 sys_clk = 0;
+
+ osc_sys_ck = clk_get(NULL, "osc_sys_ck");
+ sys_clk = clk_get_rate(osc_sys_ck);
+ clk_put(osc_sys_ck);
+
+ switch (sys_clk) {
+ case 12000000:
+ sr->clk_length = SRCLKLENGTH_12MHZ_SYSCLK;
+ break;
+ case 13000000:
+ sr->clk_length = SRCLKLENGTH_13MHZ_SYSCLK;
+ break;
+ case 19200000:
+ sr->clk_length = SRCLKLENGTH_19MHZ_SYSCLK;
+ break;
+ case 26000000:
+ sr->clk_length = SRCLKLENGTH_26MHZ_SYSCLK;
+ break;
+ case 38400000:
+ sr->clk_length = SRCLKLENGTH_38MHZ_SYSCLK;
+ break;
+ default :
+ printk(KERN_ERR "Invalid sysclk value: %d\n", sys_clk);
+ break;
+ }
+}
+
+/*
+ * TODO: once EFUSE is available, it should be used instead of these
+ * pre-calculated values.
+ */
static void sr_set_nvalues(struct omap_sr *sr)
{
-#ifdef USE_EFUSE_VALUES
- u32 n1, n2;
-#else
u32 senpval, sennval;
u32 senpgain, senngain;
u32 rnsenp, rnsenn;
-#endif

if (sr->srid == SR1) {
-#ifdef USE_EFUSE_VALUES
- /* Read values for VDD1 from EFUSE */
-#else
/* since E-Fuse Values are not available, calculating the
* reciprocal of the SenN and SenP values for SR1
*/
@@ -216,15 +267,16 @@ static void sr_set_nvalues(struct omap_sr *sr)
(rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
(rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));

+ /* XXX The clocks are enabled in the startup and NVALUE is
+ * set also there. Disabling this for now, but this could
+ * be related to dynamic sleep during boot */
+#if 0
sr_clk_enable(sr);
sr_write_reg(sr, NVALUERECIPROCAL, sr->opp3_nvalue);
sr_clk_disable(sr);
-
#endif
+
} else if (sr->srid == SR2) {
-#ifdef USE_EFUSE_VALUES
- /* Read values for VDD2 from EFUSE */
-#else
/* since E-Fuse Values are not available, calculating the
* reciprocal of the SenN and SenP values for SR2
*/
@@ -269,8 +321,6 @@ static void sr_set_nvalues(struct omap_sr *sr)
(senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
(rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
(rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
-
-#endif
}

}
@@ -281,122 +331,126 @@ static void sr_configure_vp(int srid)

if (srid == SR1) {
vpconfig = PRM_VP1_CONFIG_ERROROFFSET | PRM_VP1_CONFIG_ERRORGAIN
- | PRM_VP1_CONFIG_INITVOLTAGE | PRM_VP1_CONFIG_TIMEOUTEN;
+ | PRM_VP1_CONFIG_INITVOLTAGE
+ | PRM_VP1_CONFIG_TIMEOUTEN;

- PRM_VP1_CONFIG = vpconfig;
- PRM_VP1_VSTEPMIN = PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN |
- PRM_VP1_VSTEPMIN_VSTEPMIN;
+ __raw_writel(vpconfig, OMAP3430_PRM_VP1_CONFIG);
+ __raw_writel(PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN |
+ PRM_VP1_VSTEPMIN_VSTEPMIN,
+ OMAP3430_PRM_VP1_VSTEPMIN);

- PRM_VP1_VSTEPMAX = PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX |
- PRM_VP1_VSTEPMAX_VSTEPMAX;
+ __raw_writel(PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX |
+ PRM_VP1_VSTEPMAX_VSTEPMAX,
+ OMAP3430_PRM_VP1_VSTEPMAX);

- PRM_VP1_VLIMITTO = PRM_VP1_VLIMITTO_VDDMAX |
- PRM_VP1_VLIMITTO_VDDMIN | PRM_VP1_VLIMITTO_TIMEOUT;
+ __raw_writel(PRM_VP1_VLIMITTO_VDDMAX | PRM_VP1_VLIMITTO_VDDMIN |
+ PRM_VP1_VLIMITTO_TIMEOUT,
+ OMAP3430_PRM_VP1_VLIMITTO);

- PRM_VP1_CONFIG |= PRM_VP1_CONFIG_INITVDD;
- PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_INITVDD;
+ /* Trigger initVDD value copy to voltage processor */
+ prm_rmw_reg_bits(PRM_VP1_CONFIG_INITVDD, PRM_VP1_CONFIG_INITVDD,
+ OMAP3430_PRM_VP1_CONFIG);
+ /* Reset initVDD copy trigger bit */
+ prm_rmw_reg_bits(PRM_VP1_CONFIG_INITVDD, 0,
+ OMAP3430_PRM_VP1_CONFIG);

} else if (srid == SR2) {
vpconfig = PRM_VP2_CONFIG_ERROROFFSET | PRM_VP2_CONFIG_ERRORGAIN
- | PRM_VP2_CONFIG_INITVOLTAGE | PRM_VP2_CONFIG_TIMEOUTEN;
+ | PRM_VP2_CONFIG_INITVOLTAGE
+ | PRM_VP2_CONFIG_TIMEOUTEN;

- PRM_VP2_CONFIG = vpconfig;
- PRM_VP2_VSTEPMIN = PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN |
- PRM_VP2_VSTEPMIN_VSTEPMIN;
+ __raw_writel(vpconfig, OMAP3430_PRM_VP2_CONFIG);
+ __raw_writel(PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN |
+ PRM_VP2_VSTEPMIN_VSTEPMIN,
+ OMAP3430_PRM_VP2_VSTEPMIN);

- PRM_VP2_VSTEPMAX = PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX |
- PRM_VP2_VSTEPMAX_VSTEPMAX;
+ __raw_writel(PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX |
+ PRM_VP2_VSTEPMAX_VSTEPMAX,
+ OMAP3430_PRM_VP2_VSTEPMAX);

- PRM_VP2_VLIMITTO = PRM_VP2_VLIMITTO_VDDMAX |
- PRM_VP2_VLIMITTO_VDDMIN | PRM_VP2_VLIMITTO_TIMEOUT;
+ __raw_writel(PRM_VP2_VLIMITTO_VDDMAX | PRM_VP2_VLIMITTO_VDDMIN |
+ PRM_VP2_VLIMITTO_TIMEOUT,
+ OMAP3430_PRM_VP2_VLIMITTO);

- PRM_VP2_CONFIG |= PRM_VP2_CONFIG_INITVDD;
- PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_INITVDD;
+ /* Trigger initVDD value copy to voltage processor */
+ prm_rmw_reg_bits(PRM_VP2_CONFIG_INITVDD, PRM_VP2_CONFIG_INITVDD,
+ OMAP3430_PRM_VP2_CONFIG);
+ /* Reset initVDD copy trigger bit */
+ prm_rmw_reg_bits(PRM_VP2_CONFIG_INITVDD, 0,
+ OMAP3430_PRM_VP2_CONFIG);

}
}

static void sr_configure_vc(void)
{
- PRM_VC_SMPS_SA =
- (R_SRI2C_SLAVE_ADDR << PRM_VC_SMPS_SA1_SHIFT) |
- (R_SRI2C_SLAVE_ADDR << PRM_VC_SMPS_SA0_SHIFT);
+ __raw_writel((R_SRI2C_SLAVE_ADDR << OMAP3430_SMPS_SA1_SHIFT) |
+ (R_SRI2C_SLAVE_ADDR << OMAP3430_SMPS_SA0_SHIFT),
+ OMAP3430_PRM_VC_SMPS_SA);

- PRM_VC_SMPS_VOL_RA = (R_VDD2_SR_CONTROL << PRM_VC_SMPS_VOLRA1_SHIFT) |
- (R_VDD1_SR_CONTROL << PRM_VC_SMPS_VOLRA0_SHIFT);
+ __raw_writel((R_VDD2_SR_CONTROL << OMAP3430_VOLRA1_SHIFT) |
+ (R_VDD1_SR_CONTROL << OMAP3430_VOLRA0_SHIFT),
+ OMAP3430_PRM_VC_SMPS_VOL_RA);

- PRM_VC_CMD_VAL_0 = (PRM_VC_CMD_VAL0_ON << PRM_VC_CMD_ON_SHIFT) |
- (PRM_VC_CMD_VAL0_ONLP << PRM_VC_CMD_ONLP_SHIFT) |
- (PRM_VC_CMD_VAL0_RET << PRM_VC_CMD_RET_SHIFT) |
- (PRM_VC_CMD_VAL0_OFF << PRM_VC_CMD_OFF_SHIFT);
+ __raw_writel((OMAP3430_VC_CMD_VAL0_ON << OMAP3430_VC_CMD_ON_SHIFT) |
+ (OMAP3430_VC_CMD_VAL0_ONLP << OMAP3430_VC_CMD_ONLP_SHIFT) |
+ (OMAP3430_VC_CMD_VAL0_RET << OMAP3430_VC_CMD_RET_SHIFT) |
+ (OMAP3430_VC_CMD_VAL0_OFF << OMAP3430_VC_CMD_OFF_SHIFT),
+ OMAP3430_PRM_VC_CMD_VAL_0);

- PRM_VC_CMD_VAL_1 = (PRM_VC_CMD_VAL1_ON << PRM_VC_CMD_ON_SHIFT) |
- (PRM_VC_CMD_VAL1_ONLP << PRM_VC_CMD_ONLP_SHIFT) |
- (PRM_VC_CMD_VAL1_RET << PRM_VC_CMD_RET_SHIFT) |
- (PRM_VC_CMD_VAL1_OFF << PRM_VC_CMD_OFF_SHIFT);
+ __raw_writel((OMAP3430_VC_CMD_VAL1_ON << OMAP3430_VC_CMD_ON_SHIFT) |
+ (OMAP3430_VC_CMD_VAL1_ONLP << OMAP3430_VC_CMD_ONLP_SHIFT) |
+ (OMAP3430_VC_CMD_VAL1_RET << OMAP3430_VC_CMD_RET_SHIFT) |
+ (OMAP3430_VC_CMD_VAL1_OFF << OMAP3430_VC_CMD_OFF_SHIFT),
+ OMAP3430_PRM_VC_CMD_VAL_1);

- PRM_VC_CH_CONF = PRM_VC_CH_CONF_CMD1 | PRM_VC_CH_CONF_RAV1;
+ __raw_writel(OMAP3430_CMD1 | OMAP3430_RAV1, OMAP3430_PRM_VC_CH_CONF);

- PRM_VC_I2C_CFG = PRM_VC_I2C_CFG_MCODE | PRM_VC_I2C_CFG_HSEN
- | PRM_VC_I2C_CFG_SREN;
+ __raw_writel(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN | OMAP3430_SREN,
+ OMAP3430_PRM_VC_I2C_CFG);

/* Setup voltctrl and other setup times */
+ /* XXX CONFIG_SYSOFFMODE has not been implemented yet */
#ifdef CONFIG_SYSOFFMODE
- PRM_VOLTCTRL = PRM_VOLTCTRL_AUTO_OFF | PRM_VOLTCTRL_AUTO_RET;
- PRM_CLKSETUP = PRM_CLKSETUP_DURATION;
- PRM_VOLTSETUP1 = (PRM_VOLTSETUP_TIME2 << PRM_VOLTSETUP_TIME2_OFFSET) |
- (PRM_VOLTSETUP_TIME1 << PRM_VOLTSETUP_TIME1_OFFSET);
- PRM_VOLTOFFSET = PRM_VOLTOFFSET_DURATION;
- PRM_VOLTSETUP2 = PRM_VOLTSETUP2_DURATION;
+ __raw_writel(OMAP3430_AUTO_OFF | OMAP3430_AUTO_RET,
+ OMAP3430_PRM_VOLTCTRL);
+
+ __raw_writel(OMAP3430_CLKSETUP_DURATION, OMAP3430_PRM_CLKSETUP);
+ __raw_writel((OMAP3430_VOLTSETUP_TIME2 <<
+ OMAP3430_VOLTSETUP_TIME2_OFFSET) |
+ (OMAP3430_VOLTSETUP_TIME1 <<
+ OMAP3430_VOLTSETUP_TIME1_OFFSET),
+ OMAP3430_PRM_VOLTSETUP1);
+
+ __raw_writel(OMAP3430_VOLTOFFSET_DURATION, OMAP3430_PRM_VOLTOFFSET);
+ __raw_writel(OMAP3430_VOLTSETUP2_DURATION, OMAP3430_PRM_VOLTSETUP2);
#else
- PRM_VOLTCTRL |= PRM_VOLTCTRL_AUTO_RET;
+ prm_rmw_reg_bits(OMAP3430_AUTO_RET, OMAP3430_AUTO_RET,
+ OMAP3430_PRM_VOLTCTRL);
#endif

}

-
static void sr_configure(struct omap_sr *sr)
{
- u32 sys_clk, sr_clk_length = 0;
u32 sr_config;
u32 senp_en , senn_en;

+ if (sr->clk_length == 0)
+ sr_set_clk_length(sr);
+
senp_en = sr->senp_mod;
senn_en = sr->senn_mod;
-
- sys_clk = prcm_get_system_clock_speed();
-
- switch (sys_clk) {
- case 12000:
- sr_clk_length = SRCLKLENGTH_12MHZ_SYSCLK;
- break;
- case 13000:
- sr_clk_length = SRCLKLENGTH_13MHZ_SYSCLK;
- break;
- case 19200:
- sr_clk_length = SRCLKLENGTH_19MHZ_SYSCLK;
- break;
- case 26000:
- sr_clk_length = SRCLKLENGTH_26MHZ_SYSCLK;
- break;
- case 38400:
- sr_clk_length = SRCLKLENGTH_38MHZ_SYSCLK;
- break;
- default :
- printk(KERN_ERR "Invalid sysclk value\n");
- break;
- }
-
- DPRINTK(KERN_DEBUG "SR : sys clk %lu\n", sys_clk);
if (sr->srid == SR1) {
sr_config = SR1_SRCONFIG_ACCUMDATA |
- (sr_clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
+ (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN |
SRCONFIG_MINMAXAVG_EN |
(senn_en << SRCONFIG_SENNENABLE_SHIFT) |
(senp_en << SRCONFIG_SENPENABLE_SHIFT) |
SRCONFIG_DELAYCTRL;
-
+ DPRINTK(KERN_DEBUG "setting SRCONFIG1 to 0x%08lx\n",
+ (unsigned long int) sr_config);
sr_write_reg(sr, SRCONFIG, sr_config);

sr_write_reg(sr, AVGWEIGHT, SR1_AVGWEIGHT_SENPAVGWEIGHT |
@@ -408,18 +462,18 @@ static void sr_configure(struct omap_sr *sr)

} else if (sr->srid == SR2) {
sr_config = SR2_SRCONFIG_ACCUMDATA |
- (sr_clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
+ (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN |
SRCONFIG_MINMAXAVG_EN |
(senn_en << SRCONFIG_SENNENABLE_SHIFT) |
(senp_en << SRCONFIG_SENPENABLE_SHIFT) |
SRCONFIG_DELAYCTRL;

+ DPRINTK(KERN_DEBUG "setting SRCONFIG2 to 0x%08lx\n",
+ (unsigned long int) sr_config);
sr_write_reg(sr, SRCONFIG, sr_config);
-
sr_write_reg(sr, AVGWEIGHT, SR2_AVGWEIGHT_SENPAVGWEIGHT |
SR2_AVGWEIGHT_SENNAVGWEIGHT);
-
sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK |
SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
(SR2_ERRWEIGHT | SR2_ERRMAXLIMIT | SR2_ERRMINLIMIT));
@@ -476,7 +530,6 @@ static void sr_enable(struct omap_sr *sr, u32 target_opp_no)

if (current_nvalue == nvalue_reciprocal) {
DPRINTK("System is already at the desired voltage level\n");
- return;
}

sr_write_reg(sr, NVALUERECIPROCAL, nvalue_reciprocal);
@@ -485,18 +538,20 @@ static void sr_enable(struct omap_sr *sr, u32 target_opp_no)
sr_modify_reg(sr, ERRCONFIG,
(ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST),
(ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST));
-
if (sr->srid == SR1) {
/* Enable VP1 */
- PRM_VP1_CONFIG |= PRM_VP1_CONFIG_VPENABLE;
+ prm_rmw_reg_bits(PRM_VP1_CONFIG_VPENABLE,
+ PRM_VP1_CONFIG_VPENABLE,
+ OMAP3430_PRM_VP1_CONFIG);
} else if (sr->srid == SR2) {
/* Enable VP2 */
- PRM_VP2_CONFIG |= PRM_VP2_CONFIG_VPENABLE;
+ prm_rmw_reg_bits(PRM_VP2_CONFIG_VPENABLE,
+ PRM_VP2_CONFIG_VPENABLE,
+ OMAP3430_PRM_VP2_CONFIG);
}

/* SRCONFIG - enable SR */
sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE);
-
}

static void sr_disable(struct omap_sr *sr)
@@ -507,11 +562,13 @@ static void sr_disable(struct omap_sr *sr)
sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, ~SRCONFIG_SRENABLE);

if (sr->srid == SR1) {
- /* Enable VP1 */
- PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_VPENABLE;
+ /* Disable VP1 */
+ prm_rmw_reg_bits(PRM_VP1_CONFIG_VPENABLE, 0,
+ OMAP3430_PRM_VP1_CONFIG);
} else if (sr->srid == SR2) {
- /* Enable VP2 */
- PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_VPENABLE;
+ /* Disable VP2 */
+ prm_rmw_reg_bits(PRM_VP2_CONFIG_VPENABLE, 0,
+ OMAP3430_PRM_VP2_CONFIG);
}
}

@@ -574,16 +631,13 @@ void enable_smartreflex(int srid)

if (sr->is_autocomp_active == 1) {
if (sr->is_sr_reset == 1) {
- if (srid == SR1) {
- /* Enable SR clks */
- CM_FCLKEN_WKUP |= SR1_CLK_ENABLE;
- target_opp_no = get_opp_no(current_vdd1_opp);
+ /* Enable SR clks */
+ sr_clk_enable(sr);

- } else if (srid == SR2) {
- /* Enable SR clks */
- CM_FCLKEN_WKUP |= SR2_CLK_ENABLE;
+ if (srid == SR1)
+ target_opp_no = get_opp_no(current_vdd1_opp);
+ else if (srid == SR2)
target_opp_no = get_opp_no(current_vdd2_opp);
- }

sr_configure(sr);

@@ -602,15 +656,6 @@ void disable_smartreflex(int srid)
sr = &sr2;

if (sr->is_autocomp_active == 1) {
- if (srid == SR1) {
- /* Enable SR clk */
- CM_FCLKEN_WKUP |= SR1_CLK_ENABLE;
-
- } else if (srid == SR2) {
- /* Enable SR clk */
- CM_FCLKEN_WKUP |= SR2_CLK_ENABLE;
- }
-
if (sr->is_sr_reset == 0) {

sr->is_sr_reset = 1;
@@ -618,17 +663,16 @@ void disable_smartreflex(int srid)
sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE,
~SRCONFIG_SRENABLE);

+ /* Disable SR clk */
+ sr_clk_disable(sr);
if (sr->srid == SR1) {
- /* Disable SR clk */
- CM_FCLKEN_WKUP &= ~SR1_CLK_ENABLE;
- /* Enable VP1 */
- PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_VPENABLE;
-
+ /* Disable VP1 */
+ prm_rmw_reg_bits(PRM_VP1_CONFIG_VPENABLE, 0,
+ OMAP3430_PRM_VP1_CONFIG);
} else if (sr->srid == SR2) {
- /* Disable SR clk */
- CM_FCLKEN_WKUP &= ~SR2_CLK_ENABLE;
- /* Enable VP2 */
- PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_VPENABLE;
+ /* Disable VP2 */
+ prm_rmw_reg_bits(PRM_VP2_CONFIG_VPENABLE, 0,
+ OMAP3430_PRM_VP2_CONFIG);
}
}
}
@@ -638,7 +682,6 @@ void disable_smartreflex(int srid)
/* Voltage Scaling using SR VCBYPASS */
int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel)
{
- int ret;
int sr_status = 0;
u32 vdd, target_opp_no;
u32 vc_bypass_value;
@@ -651,39 +694,48 @@ int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel)
if (vdd == PRCM_VDD1) {
sr_status = sr_stop_vddautocomap(SR1);

- PRM_VC_CMD_VAL_0 = (PRM_VC_CMD_VAL_0 & ~PRM_VC_CMD_ON_MASK) |
- (vsel << PRM_VC_CMD_ON_SHIFT);
+ prm_rmw_reg_bits(OMAP3430_VC_CMD_ON_MASK,
+ (vsel << OMAP3430_VC_CMD_ON_SHIFT),
+ OMAP3430_PRM_VC_CMD_VAL_0);
reg_addr = R_VDD1_SR_CONTROL;

} else if (vdd == PRCM_VDD2) {
sr_status = sr_stop_vddautocomap(SR2);

- PRM_VC_CMD_VAL_1 = (PRM_VC_CMD_VAL_1 & ~PRM_VC_CMD_ON_MASK) |
- (vsel << PRM_VC_CMD_ON_SHIFT);
+ prm_rmw_reg_bits(OMAP3430_VC_CMD_ON_MASK,
+ (vsel << OMAP3430_VC_CMD_ON_SHIFT),
+ OMAP3430_PRM_VC_CMD_VAL_1);
reg_addr = R_VDD2_SR_CONTROL;
}

- vc_bypass_value = (vsel << PRM_VC_BYPASS_DATA_SHIFT) |
- (reg_addr << PRM_VC_BYPASS_REGADDR_SHIFT) |
- (R_SRI2C_SLAVE_ADDR << PRM_VC_BYPASS_SLAVEADDR_SHIFT);
+ vc_bypass_value = (vsel << OMAP3430_DATA_SHIFT) |
+ (reg_addr << OMAP3430_REGADDR_SHIFT) |
+ (R_SRI2C_SLAVE_ADDR << OMAP3430_SLAVEADDR_SHIFT);

- PRM_VC_BYPASS_VAL = vc_bypass_value;
+ __raw_writel(vc_bypass_value, OMAP3430_PRM_VC_BYPASS_VAL);

- PRM_VC_BYPASS_VAL |= PRM_VC_BYPASS_VALID;
+ vc_bypass_value = prm_rmw_reg_bits(OMAP3430_VALID, OMAP3430_VALID,
+ OMAP3430_PRM_VC_BYPASS_VAL);

- DPRINTK("%s : PRM_VC_BYPASS_VAL %X\n", __func__, PRM_VC_BYPASS_VAL);
- DPRINTK("PRM_IRQST_MPU %X\n", PRM_IRQSTATUS_MPU);
+ DPRINTK("%s : PRM_VC_BYPASS_VAL %X\n", __func__, vc_bypass_value);
+ DPRINTK("PRM_IRQST_MPU %X\n", __raw_readl(OMAP3430_PRM_IRQSTATUS_MPU));

- while ((PRM_VC_BYPASS_VAL & PRM_VC_BYPASS_VALID) != 0x0) {
- ret = loop_wait(&loop_cnt, &retries_cnt, 10);
- if (ret != PRCM_PASS) {
+ while ((vc_bypass_value & OMAP3430_VALID) != 0x0) {
+ loop_cnt++;
+ if (retries_cnt > 10) {
printk(KERN_INFO "Loop count exceeded in check SR I2C"
"write\n");
- return ret;
+ return SR_FAIL;
+ }
+ if (loop_cnt > 50) {
+ retries_cnt++;
+ loop_cnt = 0;
+ udelay(10);
}
+ vc_bypass_value = __raw_readl(OMAP3430_PRM_VC_BYPASS_VAL);
}

- omap_udelay(T2_SMPS_UPDATE_DELAY);
+ udelay(T2_SMPS_UPDATE_DELAY);

if (sr_status) {
if (vdd == PRCM_VDD1)
@@ -696,13 +748,15 @@ int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel)
}

/* Sysfs interface to select SR VDD1 auto compensation */
-static ssize_t omap_sr_vdd1_autocomp_show(struct kset *subsys, char *buf)
+static ssize_t omap_sr_vdd1_autocomp_show(struct kobject *kobj,
+ struct kobj_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", sr1.is_autocomp_active);
}

-static ssize_t omap_sr_vdd1_autocomp_store(struct kset *subsys,
- const char *buf, size_t n)
+static ssize_t omap_sr_vdd1_autocomp_store(struct kobject *kobj,
+ struct kobj_attribute *attr,
+ const char *buf, size_t n)
{
u32 current_vdd1opp_no;
unsigned short value;
@@ -722,7 +776,7 @@ static ssize_t omap_sr_vdd1_autocomp_store(struct kset *subsys,
return n;
}

-static struct subsys_attribute sr_vdd1_autocomp = {
+static struct kobj_attribute sr_vdd1_autocomp = {
.attr = {
.name = __stringify(sr_vdd1_autocomp),
.mode = 0644,
@@ -732,13 +786,15 @@ static struct subsys_attribute sr_vdd1_autocomp = {
};

/* Sysfs interface to select SR VDD2 auto compensation */
-static ssize_t omap_sr_vdd2_autocomp_show(struct kset *subsys, char *buf)
+static ssize_t omap_sr_vdd2_autocomp_show(struct kobject *kobj,
+ struct kobj_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", sr2.is_autocomp_active);
}

-static ssize_t omap_sr_vdd2_autocomp_store(struct kset *subsys,
- const char *buf, size_t n)
+static ssize_t omap_sr_vdd2_autocomp_store(struct kobject *kobj,
+ struct kobj_attribute *attr,
+ const char *buf, size_t n)
{
u32 current_vdd2opp_no;
unsigned short value;
@@ -758,7 +814,7 @@ static ssize_t omap_sr_vdd2_autocomp_store(struct kset *subsys,
return n;
}

-static struct subsys_attribute sr_vdd2_autocomp = {
+static struct kobj_attribute sr_vdd2_autocomp = {
.attr = {
.name = __stringify(sr_vdd2_autocomp),
.mode = 0644,
@@ -774,15 +830,19 @@ static int __init omap3_sr_init(void)
int ret = 0;
u8 RdReg;

-#ifdef CONFIG_ARCH_OMAP34XX
- sr1.fck = clk_get(NULL, "sr1_fck");
- if (IS_ERR(sr1.fck))
- printk(KERN_ERR "Could not get sr1_fck\n");
-
- sr2.fck = clk_get(NULL, "sr2_fck");
- if (IS_ERR(sr2.fck))
- printk(KERN_ERR "Could not get sr2_fck\n");
-#endif /* #ifdef CONFIG_ARCH_OMAP34XX */
+ if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+ current_vdd1_opp = PRCM_VDD1_OPP3;
+ current_vdd2_opp = PRCM_VDD2_OPP3;
+ } else {
+ current_vdd1_opp = PRCM_VDD1_OPP1;
+ current_vdd2_opp = PRCM_VDD1_OPP1;
+ }
+ if (cpu_is_omap34xx()) {
+ sr_clk_get(&sr1);
+ sr_clk_get(&sr2);
+ }
+ sr_set_clk_length(&sr1);
+ sr_set_clk_length(&sr2);

/* Call the VPConfig, VCConfig, set N Values. */
sr_set_nvalues(&sr1);
@@ -794,22 +854,24 @@ static int __init omap3_sr_init(void)
sr_configure_vc();

/* Enable SR on T2 */
- ret = t2_in(PM_RECEIVER, &RdReg, R_DCDC_GLOBAL_CFG);
- RdReg |= DCDC_GLOBAL_CFG_ENABLE_SRFLX;
- ret |= t2_out(PM_RECEIVER, RdReg, R_DCDC_GLOBAL_CFG);
+ ret = twl4030_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &RdReg,
+ R_DCDC_GLOBAL_CFG);

+ RdReg |= DCDC_GLOBAL_CFG_ENABLE_SRFLX;
+ ret |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, RdReg,
+ R_DCDC_GLOBAL_CFG);

printk(KERN_INFO "SmartReflex driver initialized\n");

- ret = subsys_create_file(&power_subsys, &sr_vdd1_autocomp);
+ ret = sysfs_create_file(power_kobj, &sr_vdd1_autocomp.attr);
if (ret)
- printk(KERN_ERR "subsys_create_file failed: %d\n", ret);
+ printk(KERN_ERR "sysfs_create_file failed: %d\n", ret);

- ret = subsys_create_file(&power_subsys, &sr_vdd2_autocomp);
+ ret = sysfs_create_file(power_kobj, &sr_vdd2_autocomp.attr);
if (ret)
- printk(KERN_ERR "subsys_create_file failed: %d\n", ret);
+ printk(KERN_ERR "sysfs_create_file failed: %d\n", ret);

return 0;
}

-arch_initcall(omap3_sr_init);
+late_initcall(omap3_sr_init);
--
1.5.4.3

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Koen Kooi
2008-06-01 09:17:01 UTC
Permalink
Kalle Jokiniemi
2008-06-02 06:13:23 UTC
Permalink
Hi Koen,

ext Koen Kooi wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
>
> Op 30 mei 2008, om 16:12 heeft Kalle Jokiniemi het volgende geschreven:
>
>> - Changed register accesses to use __raw_readl(), __raw_writel() and
>> prm_rmw_reg_bits() functions instread of "REG_X = REG_Y" type accesses.
>
> CC arch/arm/mach-omap2/smartreflex.o
> arch/arm/mach-omap2/smartreflex.c: In function 'sr_configure_vp':
> arch/arm/mach-omap2/smartreflex.c:351: error: implicit declaration of
> function 'prm_rmw_reg_bits'
>
> That function got replaced by prm_rmw_mod_reg_bits by:
> [PATCH 11/14] ARM: OMAP: Remove OMAP_PRM_REGADDR
>
> http://source.mvista.com/git/gitweb.cgi?p=linux-omap-2.6.git;a=commit;h=158e5d7128ed806b5b4eec0839e73727fa7a1f8a
>
>
Thanks. I'll make the changes and resend the patches.


>
>
>> - Added smartreflex.o into compilation, depends on
>> CONFIG_ARCH_OMAP34XX and
>> CONFIG_TWL4030_CORE
>
> This part doesn't apply anymore, but that's easily fixed
>

Will fix that also.

Br,
Kalle


>> Signed-off-by: Kalle Jokiniemi <ext-***@nokia.com>
>> ---
>> arch/arm/mach-omap2/Makefile | 4 +
>> arch/arm/mach-omap2/pm34xx.c | 9 +
>> arch/arm/mach-omap2/smartreflex.c | 406
>> +++++++++++++++++++++----------------
>> 3 files changed, 247 insertions(+), 172 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
>> index b617b66..6a4c7e7 100644
>> --- a/arch/arm/mach-omap2/Makefile
>> +++ b/arch/arm/mach-omap2/Makefile
>> @@ -21,6 +21,10 @@ endif
>> ifeq ($(CONFIG_ARCH_OMAP3),y)
>> obj-$(CONFIG_PM) += pm34xx.o sleep34xx.o
>> endif
>> +
>> +ifeq ($(CONFIG_ARCH_OMAP34XX),y)
>> +obj-$(CONFIG_TWL4030_CORE) += smartreflex.o
>> +endif
>> obj-$(CONFIG_PM_DEBUG) += pm-debug.o
>>
>> # Clock framework
>> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
>> index a1bfb30..fbba2f3 100644
>> --- a/arch/arm/mach-omap2/pm34xx.c
>> +++ b/arch/arm/mach-omap2/pm34xx.c
>> @@ -36,6 +36,7 @@
>>
>> #include "prm.h"
>> #include "pm.h"
>> +#include "smartreflex.h"
>>
>> struct power_state {
>> struct powerdomain *pwrdm;
>> @@ -243,6 +244,10 @@ static int omap3_pm_suspend(void)
>> struct power_state *pwrst;
>> int state, ret = 0;
>>
>> + /* XXX Disable smartreflex before entering suspend */
>> + disable_smartreflex(SR1);
>> + disable_smartreflex(SR2);
>> +
>> /* Read current next_pwrsts */
>> list_for_each_entry(pwrst, &pwrst_list, node)
>> pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
>> @@ -274,6 +279,10 @@ restore:
>> printk(KERN_INFO "Successfully put all powerdomains "
>> "to target state\n");
>>
>> + /* XXX Enable smartreflex after suspend */
>> + enable_smartreflex(SR1);
>> + enable_smartreflex(SR2);
>> +
>> return ret;
>> }
>>
>> diff --git a/arch/arm/mach-omap2/smartreflex.c
>> b/arch/arm/mach-omap2/smartreflex.c
>> index dae7460..068944c 100644
>> --- a/arch/arm/mach-omap2/smartreflex.c
>> +++ b/arch/arm/mach-omap2/smartreflex.c
>> @@ -3,6 +3,9 @@
>> *
>> * OMAP34XX SmartReflex Voltage Control
>> *
>> + * Copyright (C) 2008 Nokia Corporation
>> + * Kalle Jokiniemi
>> + *
>> * Copyright (C) 2007 Texas Instruments, Inc.
>> * Lesly A M <***@ti.com>
>> *
>> @@ -20,13 +23,14 @@
>> #include <linux/err.h>
>> #include <linux/clk.h>
>> #include <linux/sysfs.h>
>> -
>> -#include <asm/arch/prcm.h>
>> -#include <asm/arch/power_companion.h>
>> +#include <linux/kobject.h>
>> +#include <linux/i2c/twl4030.h>
>> #include <linux/io.h>
>>
>> -#include "prcm-regs.h"
>> +#include <asm/arch/omap34xx.h>
>> +
>> #include "smartreflex.h"
>> +#include "prm-regbits-34xx.h"
>>
>>
>> /* #define DEBUG_SR 1 */
>> @@ -37,11 +41,16 @@
>> # define DPRINTK(fmt, args...)
>> #endif
>>
>> +/* XXX: These should be relocated where-ever the OPP implementation
>> will be */
>> +u32 current_vdd1_opp;
>> +u32 current_vdd2_opp;
>> +
>> struct omap_sr{
>> int srid;
>> int is_sr_reset;
>> int is_autocomp_active;
>> struct clk *fck;
>> + u32 clk_length;
>> u32 req_opp_no;
>> u32 opp1_nvalue, opp2_nvalue, opp3_nvalue, opp4_nvalue, opp5_nvalue;
>> u32 senp_mod, senn_mod;
>> @@ -53,6 +62,7 @@ static struct omap_sr sr1 = {
>> .srid = SR1,
>> .is_sr_reset = 1,
>> .is_autocomp_active = 0,
>> + .clk_length = 0,
>> .srbase_addr = OMAP34XX_SR1_BASE,
>> };
>>
>> @@ -60,6 +70,7 @@ static struct omap_sr sr2 = {
>> .srid = SR2,
>> .is_sr_reset = 1,
>> .is_autocomp_active = 0,
>> + .clk_length = 0,
>> .srbase_addr = OMAP34XX_SR2_BASE,
>> };
>>
>> @@ -85,8 +96,6 @@ static inline u32 sr_read_reg(struct omap_sr *sr,
>> int offset)
>> return omap_readl(sr->srbase_addr + offset);
>> }
>>
>> -
>> -#ifndef USE_EFUSE_VALUES
>> static void cal_reciprocal(u32 sensor, u32 *sengain, u32 *rnsen)
>> {
>> u32 gn, rn, mul;
>> @@ -100,7 +109,21 @@ static void cal_reciprocal(u32 sensor, u32
>> *sengain, u32 *rnsen)
>> }
>> }
>> }
>> -#endif
>> +
>> +static void sr_clk_get(struct omap_sr *sr)
>> +{
>> + if (sr->srid == SR1) {
>> + sr->fck = clk_get(NULL, "sr1_fck");
>> + if (IS_ERR(sr->fck))
>> + printk(KERN_ERR "Could not get sr1_fck\n");
>> +
>> + } else if (sr->srid == SR2) {
>> + sr->fck = clk_get(NULL, "sr2_fck");
>> + if (IS_ERR(sr->fck))
>> + printk(KERN_ERR "Could not get sr2_fck\n");
>> +
>> + }
>> +}
>>
>> static int sr_clk_enable(struct omap_sr *sr)
>> {
>> @@ -131,20 +154,48 @@ static int sr_clk_disable(struct omap_sr *sr)
>> return 0;
>> }
>>
>> +static void sr_set_clk_length(struct omap_sr *sr)
>> +{
>> + struct clk *osc_sys_ck;
>> + u32 sys_clk = 0;
>> +
>> + osc_sys_ck = clk_get(NULL, "osc_sys_ck");
>> + sys_clk = clk_get_rate(osc_sys_ck);
>> + clk_put(osc_sys_ck);
>> +
>> + switch (sys_clk) {
>> + case 12000000:
>> + sr->clk_length = SRCLKLENGTH_12MHZ_SYSCLK;
>> + break;
>> + case 13000000:
>> + sr->clk_length = SRCLKLENGTH_13MHZ_SYSCLK;
>> + break;
>> + case 19200000:
>> + sr->clk_length = SRCLKLENGTH_19MHZ_SYSCLK;
>> + break;
>> + case 26000000:
>> + sr->clk_length = SRCLKLENGTH_26MHZ_SYSCLK;
>> + break;
>> + case 38400000:
>> + sr->clk_length = SRCLKLENGTH_38MHZ_SYSCLK;
>> + break;
>> + default :
>> + printk(KERN_ERR "Invalid sysclk value: %d\n", sys_clk);
>> + break;
>> + }
>> +}
>> +
>> +/*
>> + * TODO: once EFUSE is available, it should be used instead of these
>> + * pre-calculated values.
>> + */
>> static void sr_set_nvalues(struct omap_sr *sr)
>> {
>> -#ifdef USE_EFUSE_VALUES
>> - u32 n1, n2;
>> -#else
>> u32 senpval, sennval;
>> u32 senpgain, senngain;
>> u32 rnsenp, rnsenn;
>> -#endif
>>
>> if (sr->srid == SR1) {
>> -#ifdef USE_EFUSE_VALUES
>> - /* Read values for VDD1 from EFUSE */
>> -#else
>> /* since E-Fuse Values are not available, calculating the
>> * reciprocal of the SenN and SenP values for SR1
>> */
>> @@ -216,15 +267,16 @@ static void sr_set_nvalues(struct omap_sr *sr)
>> (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
>> (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
>>
>> + /* XXX The clocks are enabled in the startup and NVALUE is
>> + * set also there. Disabling this for now, but this could
>> + * be related to dynamic sleep during boot */
>> +#if 0
>> sr_clk_enable(sr);
>> sr_write_reg(sr, NVALUERECIPROCAL, sr->opp3_nvalue);
>> sr_clk_disable(sr);
>> -
>> #endif
>> +
>> } else if (sr->srid == SR2) {
>> -#ifdef USE_EFUSE_VALUES
>> - /* Read values for VDD2 from EFUSE */
>> -#else
>> /* since E-Fuse Values are not available, calculating the
>> * reciprocal of the SenN and SenP values for SR2
>> */
>> @@ -269,8 +321,6 @@ static void sr_set_nvalues(struct omap_sr *sr)
>> (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
>> (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
>> (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
>> -
>> -#endif
>> }
>>
>> }
>> @@ -281,122 +331,126 @@ static void sr_configure_vp(int srid)
>>
>> if (srid == SR1) {
>> vpconfig = PRM_VP1_CONFIG_ERROROFFSET | PRM_VP1_CONFIG_ERRORGAIN
>> - | PRM_VP1_CONFIG_INITVOLTAGE | PRM_VP1_CONFIG_TIMEOUTEN;
>> + | PRM_VP1_CONFIG_INITVOLTAGE
>> + | PRM_VP1_CONFIG_TIMEOUTEN;
>>
>> - PRM_VP1_CONFIG = vpconfig;
>> - PRM_VP1_VSTEPMIN = PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN |
>> - PRM_VP1_VSTEPMIN_VSTEPMIN;
>> + __raw_writel(vpconfig, OMAP3430_PRM_VP1_CONFIG);
>> + __raw_writel(PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN |
>> + PRM_VP1_VSTEPMIN_VSTEPMIN,
>> + OMAP3430_PRM_VP1_VSTEPMIN);
>>
>> - PRM_VP1_VSTEPMAX = PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX |
>> - PRM_VP1_VSTEPMAX_VSTEPMAX;
>> + __raw_writel(PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX |
>> + PRM_VP1_VSTEPMAX_VSTEPMAX,
>> + OMAP3430_PRM_VP1_VSTEPMAX);
>>
>> - PRM_VP1_VLIMITTO = PRM_VP1_VLIMITTO_VDDMAX |
>> - PRM_VP1_VLIMITTO_VDDMIN | PRM_VP1_VLIMITTO_TIMEOUT;
>> + __raw_writel(PRM_VP1_VLIMITTO_VDDMAX |
>> PRM_VP1_VLIMITTO_VDDMIN |
>> + PRM_VP1_VLIMITTO_TIMEOUT,
>> + OMAP3430_PRM_VP1_VLIMITTO);
>>
>> - PRM_VP1_CONFIG |= PRM_VP1_CONFIG_INITVDD;
>> - PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_INITVDD;
>> + /* Trigger initVDD value copy to voltage processor */
>> + prm_rmw_reg_bits(PRM_VP1_CONFIG_INITVDD,
>> PRM_VP1_CONFIG_INITVDD,
>> + OMAP3430_PRM_VP1_CONFIG);
>> + /* Reset initVDD copy trigger bit */
>> + prm_rmw_reg_bits(PRM_VP1_CONFIG_INITVDD, 0,
>> + OMAP3430_PRM_VP1_CONFIG);
>>
>> } else if (srid == SR2) {
>> vpconfig = PRM_VP2_CONFIG_ERROROFFSET | PRM_VP2_CONFIG_ERRORGAIN
>> - | PRM_VP2_CONFIG_INITVOLTAGE | PRM_VP2_CONFIG_TIMEOUTEN;
>> + | PRM_VP2_CONFIG_INITVOLTAGE
>> + | PRM_VP2_CONFIG_TIMEOUTEN;
>>
>> - PRM_VP2_CONFIG = vpconfig;
>> - PRM_VP2_VSTEPMIN = PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN |
>> - PRM_VP2_VSTEPMIN_VSTEPMIN;
>> + __raw_writel(vpconfig, OMAP3430_PRM_VP2_CONFIG);
>> + __raw_writel(PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN |
>> + PRM_VP2_VSTEPMIN_VSTEPMIN,
>> + OMAP3430_PRM_VP2_VSTEPMIN);
>>
>> - PRM_VP2_VSTEPMAX = PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX |
>> - PRM_VP2_VSTEPMAX_VSTEPMAX;
>> + __raw_writel(PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX |
>> + PRM_VP2_VSTEPMAX_VSTEPMAX,
>> + OMAP3430_PRM_VP2_VSTEPMAX);
>>
>> - PRM_VP2_VLIMITTO = PRM_VP2_VLIMITTO_VDDMAX |
>> - PRM_VP2_VLIMITTO_VDDMIN | PRM_VP2_VLIMITTO_TIMEOUT;
>> + __raw_writel(PRM_VP2_VLIMITTO_VDDMAX |
>> PRM_VP2_VLIMITTO_VDDMIN |
>> + PRM_VP2_VLIMITTO_TIMEOUT,
>> + OMAP3430_PRM_VP2_VLIMITTO);
>>
>> - PRM_VP2_CONFIG |= PRM_VP2_CONFIG_INITVDD;
>> - PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_INITVDD;
>> + /* Trigger initVDD value copy to voltage processor */
>> + prm_rmw_reg_bits(PRM_VP2_CONFIG_INITVDD,
>> PRM_VP2_CONFIG_INITVDD,
>> + OMAP3430_PRM_VP2_CONFIG);
>> + /* Reset initVDD copy trigger bit */
>> + prm_rmw_reg_bits(PRM_VP2_CONFIG_INITVDD, 0,
>> + OMAP3430_PRM_VP2_CONFIG);
>>
>> }
>> }
>>
>> static void sr_configure_vc(void)
>> {
>> - PRM_VC_SMPS_SA =
>> - (R_SRI2C_SLAVE_ADDR << PRM_VC_SMPS_SA1_SHIFT) |
>> - (R_SRI2C_SLAVE_ADDR << PRM_VC_SMPS_SA0_SHIFT);
>> + __raw_writel((R_SRI2C_SLAVE_ADDR << OMAP3430_SMPS_SA1_SHIFT) |
>> + (R_SRI2C_SLAVE_ADDR << OMAP3430_SMPS_SA0_SHIFT),
>> + OMAP3430_PRM_VC_SMPS_SA);
>>
>> - PRM_VC_SMPS_VOL_RA = (R_VDD2_SR_CONTROL <<
>> PRM_VC_SMPS_VOLRA1_SHIFT) |
>> - (R_VDD1_SR_CONTROL << PRM_VC_SMPS_VOLRA0_SHIFT);
>> + __raw_writel((R_VDD2_SR_CONTROL << OMAP3430_VOLRA1_SHIFT) |
>> + (R_VDD1_SR_CONTROL << OMAP3430_VOLRA0_SHIFT),
>> + OMAP3430_PRM_VC_SMPS_VOL_RA);
>>
>> - PRM_VC_CMD_VAL_0 = (PRM_VC_CMD_VAL0_ON << PRM_VC_CMD_ON_SHIFT) |
>> - (PRM_VC_CMD_VAL0_ONLP << PRM_VC_CMD_ONLP_SHIFT) |
>> - (PRM_VC_CMD_VAL0_RET << PRM_VC_CMD_RET_SHIFT) |
>> - (PRM_VC_CMD_VAL0_OFF << PRM_VC_CMD_OFF_SHIFT);
>> + __raw_writel((OMAP3430_VC_CMD_VAL0_ON <<
>> OMAP3430_VC_CMD_ON_SHIFT) |
>> + (OMAP3430_VC_CMD_VAL0_ONLP << OMAP3430_VC_CMD_ONLP_SHIFT) |
>> + (OMAP3430_VC_CMD_VAL0_RET << OMAP3430_VC_CMD_RET_SHIFT) |
>> + (OMAP3430_VC_CMD_VAL0_OFF << OMAP3430_VC_CMD_OFF_SHIFT),
>> + OMAP3430_PRM_VC_CMD_VAL_0);
>>
>> - PRM_VC_CMD_VAL_1 = (PRM_VC_CMD_VAL1_ON << PRM_VC_CMD_ON_SHIFT) |
>> - (PRM_VC_CMD_VAL1_ONLP << PRM_VC_CMD_ONLP_SHIFT) |
>> - (PRM_VC_CMD_VAL1_RET << PRM_VC_CMD_RET_SHIFT) |
>> - (PRM_VC_CMD_VAL1_OFF << PRM_VC_CMD_OFF_SHIFT);
>> + __raw_writel((OMAP3430_VC_CMD_VAL1_ON <<
>> OMAP3430_VC_CMD_ON_SHIFT) |
>> + (OMAP3430_VC_CMD_VAL1_ONLP << OMAP3430_VC_CMD_ONLP_SHIFT) |
>> + (OMAP3430_VC_CMD_VAL1_RET << OMAP3430_VC_CMD_RET_SHIFT) |
>> + (OMAP3430_VC_CMD_VAL1_OFF << OMAP3430_VC_CMD_OFF_SHIFT),
>> + OMAP3430_PRM_VC_CMD_VAL_1);
>>
>> - PRM_VC_CH_CONF = PRM_VC_CH_CONF_CMD1 | PRM_VC_CH_CONF_RAV1;
>> + __raw_writel(OMAP3430_CMD1 | OMAP3430_RAV1,
>> OMAP3430_PRM_VC_CH_CONF);
>>
>> - PRM_VC_I2C_CFG = PRM_VC_I2C_CFG_MCODE | PRM_VC_I2C_CFG_HSEN
>> - | PRM_VC_I2C_CFG_SREN;
>> + __raw_writel(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN | OMAP3430_SREN,
>> + OMAP3430_PRM_VC_I2C_CFG);
>>
>> /* Setup voltctrl and other setup times */
>> + /* XXX CONFIG_SYSOFFMODE has not been implemented yet */
>> #ifdef CONFIG_SYSOFFMODE
>> - PRM_VOLTCTRL = PRM_VOLTCTRL_AUTO_OFF | PRM_VOLTCTRL_AUTO_RET;
>> - PRM_CLKSETUP = PRM_CLKSETUP_DURATION;
>> - PRM_VOLTSETUP1 = (PRM_VOLTSETUP_TIME2 <<
>> PRM_VOLTSETUP_TIME2_OFFSET) |
>> - (PRM_VOLTSETUP_TIME1 << PRM_VOLTSETUP_TIME1_OFFSET);
>> - PRM_VOLTOFFSET = PRM_VOLTOFFSET_DURATION;
>> - PRM_VOLTSETUP2 = PRM_VOLTSETUP2_DURATION;
>> + __raw_writel(OMAP3430_AUTO_OFF | OMAP3430_AUTO_RET,
>> + OMAP3430_PRM_VOLTCTRL);
>> +
>> + __raw_writel(OMAP3430_CLKSETUP_DURATION, OMAP3430_PRM_CLKSETUP);
>> + __raw_writel((OMAP3430_VOLTSETUP_TIME2 <<
>> + OMAP3430_VOLTSETUP_TIME2_OFFSET) |
>> + (OMAP3430_VOLTSETUP_TIME1 <<
>> + OMAP3430_VOLTSETUP_TIME1_OFFSET),
>> + OMAP3430_PRM_VOLTSETUP1);
>> +
>> + __raw_writel(OMAP3430_VOLTOFFSET_DURATION,
>> OMAP3430_PRM_VOLTOFFSET);
>> + __raw_writel(OMAP3430_VOLTSETUP2_DURATION,
>> OMAP3430_PRM_VOLTSETUP2);
>> #else
>> - PRM_VOLTCTRL |= PRM_VOLTCTRL_AUTO_RET;
>> + prm_rmw_reg_bits(OMAP3430_AUTO_RET, OMAP3430_AUTO_RET,
>> + OMAP3430_PRM_VOLTCTRL);
>> #endif
>>
>> }
>>
>> -
>> static void sr_configure(struct omap_sr *sr)
>> {
>> - u32 sys_clk, sr_clk_length = 0;
>> u32 sr_config;
>> u32 senp_en , senn_en;
>>
>> + if (sr->clk_length == 0)
>> + sr_set_clk_length(sr);
>> +
>> senp_en = sr->senp_mod;
>> senn_en = sr->senn_mod;
>> -
>> - sys_clk = prcm_get_system_clock_speed();
>> -
>> - switch (sys_clk) {
>> - case 12000:
>> - sr_clk_length = SRCLKLENGTH_12MHZ_SYSCLK;
>> - break;
>> - case 13000:
>> - sr_clk_length = SRCLKLENGTH_13MHZ_SYSCLK;
>> - break;
>> - case 19200:
>> - sr_clk_length = SRCLKLENGTH_19MHZ_SYSCLK;
>> - break;
>> - case 26000:
>> - sr_clk_length = SRCLKLENGTH_26MHZ_SYSCLK;
>> - break;
>> - case 38400:
>> - sr_clk_length = SRCLKLENGTH_38MHZ_SYSCLK;
>> - break;
>> - default :
>> - printk(KERN_ERR "Invalid sysclk value\n");
>> - break;
>> - }
>> -
>> - DPRINTK(KERN_DEBUG "SR : sys clk %lu\n", sys_clk);
>> if (sr->srid == SR1) {
>> sr_config = SR1_SRCONFIG_ACCUMDATA |
>> - (sr_clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
>> + (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
>> SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN |
>> SRCONFIG_MINMAXAVG_EN |
>> (senn_en << SRCONFIG_SENNENABLE_SHIFT) |
>> (senp_en << SRCONFIG_SENPENABLE_SHIFT) |
>> SRCONFIG_DELAYCTRL;
>> -
>> + DPRINTK(KERN_DEBUG "setting SRCONFIG1 to 0x%08lx\n",
>> + (unsigned long int) sr_config);
>> sr_write_reg(sr, SRCONFIG, sr_config);
>>
>> sr_write_reg(sr, AVGWEIGHT, SR1_AVGWEIGHT_SENPAVGWEIGHT |
>> @@ -408,18 +462,18 @@ static void sr_configure(struct omap_sr *sr)
>>
>> } else if (sr->srid == SR2) {
>> sr_config = SR2_SRCONFIG_ACCUMDATA |
>> - (sr_clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
>> + (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
>> SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN |
>> SRCONFIG_MINMAXAVG_EN |
>> (senn_en << SRCONFIG_SENNENABLE_SHIFT) |
>> (senp_en << SRCONFIG_SENPENABLE_SHIFT) |
>> SRCONFIG_DELAYCTRL;
>>
>> + DPRINTK(KERN_DEBUG "setting SRCONFIG2 to 0x%08lx\n",
>> + (unsigned long int) sr_config);
>> sr_write_reg(sr, SRCONFIG, sr_config);
>> -
>> sr_write_reg(sr, AVGWEIGHT, SR2_AVGWEIGHT_SENPAVGWEIGHT |
>> SR2_AVGWEIGHT_SENNAVGWEIGHT);
>> -
>> sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK |
>> SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
>> (SR2_ERRWEIGHT | SR2_ERRMAXLIMIT | SR2_ERRMINLIMIT));
>> @@ -476,7 +530,6 @@ static void sr_enable(struct omap_sr *sr, u32
>> target_opp_no)
>>
>> if (current_nvalue == nvalue_reciprocal) {
>> DPRINTK("System is already at the desired voltage level\n");
>> - return;
>> }
>>
>> sr_write_reg(sr, NVALUERECIPROCAL, nvalue_reciprocal);
>> @@ -485,18 +538,20 @@ static void sr_enable(struct omap_sr *sr, u32
>> target_opp_no)
>> sr_modify_reg(sr, ERRCONFIG,
>> (ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST),
>> (ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST));
>> -
>> if (sr->srid == SR1) {
>> /* Enable VP1 */
>> - PRM_VP1_CONFIG |= PRM_VP1_CONFIG_VPENABLE;
>> + prm_rmw_reg_bits(PRM_VP1_CONFIG_VPENABLE,
>> + PRM_VP1_CONFIG_VPENABLE,
>> + OMAP3430_PRM_VP1_CONFIG);
>> } else if (sr->srid == SR2) {
>> /* Enable VP2 */
>> - PRM_VP2_CONFIG |= PRM_VP2_CONFIG_VPENABLE;
>> + prm_rmw_reg_bits(PRM_VP2_CONFIG_VPENABLE,
>> + PRM_VP2_CONFIG_VPENABLE,
>> + OMAP3430_PRM_VP2_CONFIG);
>> }
>>
>> /* SRCONFIG - enable SR */
>> sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE);
>> -
>> }
>>
>> static void sr_disable(struct omap_sr *sr)
>> @@ -507,11 +562,13 @@ static void sr_disable(struct omap_sr *sr)
>> sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, ~SRCONFIG_SRENABLE);
>>
>> if (sr->srid == SR1) {
>> - /* Enable VP1 */
>> - PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_VPENABLE;
>> + /* Disable VP1 */
>> + prm_rmw_reg_bits(PRM_VP1_CONFIG_VPENABLE, 0,
>> + OMAP3430_PRM_VP1_CONFIG);
>> } else if (sr->srid == SR2) {
>> - /* Enable VP2 */
>> - PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_VPENABLE;
>> + /* Disable VP2 */
>> + prm_rmw_reg_bits(PRM_VP2_CONFIG_VPENABLE, 0,
>> + OMAP3430_PRM_VP2_CONFIG);
>> }
>> }
>>
>> @@ -574,16 +631,13 @@ void enable_smartreflex(int srid)
>>
>> if (sr->is_autocomp_active == 1) {
>> if (sr->is_sr_reset == 1) {
>> - if (srid == SR1) {
>> - /* Enable SR clks */
>> - CM_FCLKEN_WKUP |= SR1_CLK_ENABLE;
>> - target_opp_no = get_opp_no(current_vdd1_opp);
>> + /* Enable SR clks */
>> + sr_clk_enable(sr);
>>
>> - } else if (srid == SR2) {
>> - /* Enable SR clks */
>> - CM_FCLKEN_WKUP |= SR2_CLK_ENABLE;
>> + if (srid == SR1)
>> + target_opp_no = get_opp_no(current_vdd1_opp);
>> + else if (srid == SR2)
>> target_opp_no = get_opp_no(current_vdd2_opp);
>> - }
>>
>> sr_configure(sr);
>>
>> @@ -602,15 +656,6 @@ void disable_smartreflex(int srid)
>> sr = &sr2;
>>
>> if (sr->is_autocomp_active == 1) {
>> - if (srid == SR1) {
>> - /* Enable SR clk */
>> - CM_FCLKEN_WKUP |= SR1_CLK_ENABLE;
>> -
>> - } else if (srid == SR2) {
>> - /* Enable SR clk */
>> - CM_FCLKEN_WKUP |= SR2_CLK_ENABLE;
>> - }
>> -
>> if (sr->is_sr_reset == 0) {
>>
>> sr->is_sr_reset = 1;
>> @@ -618,17 +663,16 @@ void disable_smartreflex(int srid)
>> sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE,
>> ~SRCONFIG_SRENABLE);
>>
>> + /* Disable SR clk */
>> + sr_clk_disable(sr);
>> if (sr->srid == SR1) {
>> - /* Disable SR clk */
>> - CM_FCLKEN_WKUP &= ~SR1_CLK_ENABLE;
>> - /* Enable VP1 */
>> - PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_VPENABLE;
>> -
>> + /* Disable VP1 */
>> + prm_rmw_reg_bits(PRM_VP1_CONFIG_VPENABLE, 0,
>> + OMAP3430_PRM_VP1_CONFIG);
>> } else if (sr->srid == SR2) {
>> - /* Disable SR clk */
>> - CM_FCLKEN_WKUP &= ~SR2_CLK_ENABLE;
>> - /* Enable VP2 */
>> - PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_VPENABLE;
>> + /* Disable VP2 */
>> + prm_rmw_reg_bits(PRM_VP2_CONFIG_VPENABLE, 0,
>> + OMAP3430_PRM_VP2_CONFIG);
>> }
>> }
>> }
>> @@ -638,7 +682,6 @@ void disable_smartreflex(int srid)
>> /* Voltage Scaling using SR VCBYPASS */
>> int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel)
>> {
>> - int ret;
>> int sr_status = 0;
>> u32 vdd, target_opp_no;
>> u32 vc_bypass_value;
>> @@ -651,39 +694,48 @@ int sr_voltagescale_vcbypass(u32 target_opp, u8
>> vsel)
>> if (vdd == PRCM_VDD1) {
>> sr_status = sr_stop_vddautocomap(SR1);
>>
>> - PRM_VC_CMD_VAL_0 = (PRM_VC_CMD_VAL_0 & ~PRM_VC_CMD_ON_MASK) |
>> - (vsel << PRM_VC_CMD_ON_SHIFT);
>> + prm_rmw_reg_bits(OMAP3430_VC_CMD_ON_MASK,
>> + (vsel << OMAP3430_VC_CMD_ON_SHIFT),
>> + OMAP3430_PRM_VC_CMD_VAL_0);
>> reg_addr = R_VDD1_SR_CONTROL;
>>
>> } else if (vdd == PRCM_VDD2) {
>> sr_status = sr_stop_vddautocomap(SR2);
>>
>> - PRM_VC_CMD_VAL_1 = (PRM_VC_CMD_VAL_1 & ~PRM_VC_CMD_ON_MASK) |
>> - (vsel << PRM_VC_CMD_ON_SHIFT);
>> + prm_rmw_reg_bits(OMAP3430_VC_CMD_ON_MASK,
>> + (vsel << OMAP3430_VC_CMD_ON_SHIFT),
>> + OMAP3430_PRM_VC_CMD_VAL_1);
>> reg_addr = R_VDD2_SR_CONTROL;
>> }
>>
>> - vc_bypass_value = (vsel << PRM_VC_BYPASS_DATA_SHIFT) |
>> - (reg_addr << PRM_VC_BYPASS_REGADDR_SHIFT) |
>> - (R_SRI2C_SLAVE_ADDR << PRM_VC_BYPASS_SLAVEADDR_SHIFT);
>> + vc_bypass_value = (vsel << OMAP3430_DATA_SHIFT) |
>> + (reg_addr << OMAP3430_REGADDR_SHIFT) |
>> + (R_SRI2C_SLAVE_ADDR << OMAP3430_SLAVEADDR_SHIFT);
>>
>> - PRM_VC_BYPASS_VAL = vc_bypass_value;
>> + __raw_writel(vc_bypass_value, OMAP3430_PRM_VC_BYPASS_VAL);
>>
>> - PRM_VC_BYPASS_VAL |= PRM_VC_BYPASS_VALID;
>> + vc_bypass_value = prm_rmw_reg_bits(OMAP3430_VALID, OMAP3430_VALID,
>> + OMAP3430_PRM_VC_BYPASS_VAL);
>>
>> - DPRINTK("%s : PRM_VC_BYPASS_VAL %X\n", __func__,
>> PRM_VC_BYPASS_VAL);
>> - DPRINTK("PRM_IRQST_MPU %X\n", PRM_IRQSTATUS_MPU);
>> + DPRINTK("%s : PRM_VC_BYPASS_VAL %X\n", __func__, vc_bypass_value);
>> + DPRINTK("PRM_IRQST_MPU %X\n",
>> __raw_readl(OMAP3430_PRM_IRQSTATUS_MPU));
>>
>> - while ((PRM_VC_BYPASS_VAL & PRM_VC_BYPASS_VALID) != 0x0) {
>> - ret = loop_wait(&loop_cnt, &retries_cnt, 10);
>> - if (ret != PRCM_PASS) {
>> + while ((vc_bypass_value & OMAP3430_VALID) != 0x0) {
>> + loop_cnt++;
>> + if (retries_cnt > 10) {
>> printk(KERN_INFO "Loop count exceeded in check SR I2C"
>> "write\n");
>> - return ret;
>> + return SR_FAIL;
>> + }
>> + if (loop_cnt > 50) {
>> + retries_cnt++;
>> + loop_cnt = 0;
>> + udelay(10);
>> }
>> + vc_bypass_value = __raw_readl(OMAP3430_PRM_VC_BYPASS_VAL);
>> }
>>
>> - omap_udelay(T2_SMPS_UPDATE_DELAY);
>> + udelay(T2_SMPS_UPDATE_DELAY);
>>
>> if (sr_status) {
>> if (vdd == PRCM_VDD1)
>> @@ -696,13 +748,15 @@ int sr_voltagescale_vcbypass(u32 target_opp, u8
>> vsel)
>> }
>>
>> /* Sysfs interface to select SR VDD1 auto compensation */
>> -static ssize_t omap_sr_vdd1_autocomp_show(struct kset *subsys, char
>> *buf)
>> +static ssize_t omap_sr_vdd1_autocomp_show(struct kobject *kobj,
>> + struct kobj_attribute *attr, char *buf)
>> {
>> return sprintf(buf, "%d\n", sr1.is_autocomp_active);
>> }
>>
>> -static ssize_t omap_sr_vdd1_autocomp_store(struct kset *subsys,
>> - const char *buf, size_t n)
>> +static ssize_t omap_sr_vdd1_autocomp_store(struct kobject *kobj,
>> + struct kobj_attribute *attr,
>> + const char *buf, size_t n)
>> {
>> u32 current_vdd1opp_no;
>> unsigned short value;
>> @@ -722,7 +776,7 @@ static ssize_t omap_sr_vdd1_autocomp_store(struct
>> kset *subsys,
>> return n;
>> }
>>
>> -static struct subsys_attribute sr_vdd1_autocomp = {
>> +static struct kobj_attribute sr_vdd1_autocomp = {
>> .attr = {
>> .name = __stringify(sr_vdd1_autocomp),
>> .mode = 0644,
>> @@ -732,13 +786,15 @@ static struct subsys_attribute sr_vdd1_autocomp
>> = {
>> };
>>
>> /* Sysfs interface to select SR VDD2 auto compensation */
>> -static ssize_t omap_sr_vdd2_autocomp_show(struct kset *subsys, char
>> *buf)
>> +static ssize_t omap_sr_vdd2_autocomp_show(struct kobject *kobj,
>> + struct kobj_attribute *attr, char *buf)
>> {
>> return sprintf(buf, "%d\n", sr2.is_autocomp_active);
>> }
>>
>> -static ssize_t omap_sr_vdd2_autocomp_store(struct kset *subsys,
>> - const char *buf, size_t n)
>> +static ssize_t omap_sr_vdd2_autocomp_store(struct kobject *kobj,
>> + struct kobj_attribute *attr,
>> + const char *buf, size_t n)
>> {
>> u32 current_vdd2opp_no;
>> unsigned short value;
>> @@ -758,7 +814,7 @@ static ssize_t omap_sr_vdd2_autocomp_store(struct
>> kset *subsys,
>> return n;
>> }
>>
>> -static struct subsys_attribute sr_vdd2_autocomp = {
>> +static struct kobj_attribute sr_vdd2_autocomp = {
>> .attr = {
>> .name = __stringify(sr_vdd2_autocomp),
>> .mode = 0644,
>> @@ -774,15 +830,19 @@ static int __init omap3_sr_init(void)
>> int ret = 0;
>> u8 RdReg;
>>
>> -#ifdef CONFIG_ARCH_OMAP34XX
>> - sr1.fck = clk_get(NULL, "sr1_fck");
>> - if (IS_ERR(sr1.fck))
>> - printk(KERN_ERR "Could not get sr1_fck\n");
>> -
>> - sr2.fck = clk_get(NULL, "sr2_fck");
>> - if (IS_ERR(sr2.fck))
>> - printk(KERN_ERR "Could not get sr2_fck\n");
>> -#endif /* #ifdef CONFIG_ARCH_OMAP34XX */
>> + if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
>> + current_vdd1_opp = PRCM_VDD1_OPP3;
>> + current_vdd2_opp = PRCM_VDD2_OPP3;
>> + } else {
>> + current_vdd1_opp = PRCM_VDD1_OPP1;
>> + current_vdd2_opp = PRCM_VDD1_OPP1;
>> + }
>> + if (cpu_is_omap34xx()) {
>> + sr_clk_get(&sr1);
>> + sr_clk_get(&sr2);
>> + }
>> + sr_set_clk_length(&sr1);
>> + sr_set_clk_length(&sr2);
>>
>> /* Call the VPConfig, VCConfig, set N Values. */
>> sr_set_nvalues(&sr1);
>> @@ -794,22 +854,24 @@ static int __init omap3_sr_init(void)
>> sr_configure_vc();
>>
>> /* Enable SR on T2 */
>> - ret = t2_in(PM_RECEIVER, &RdReg, R_DCDC_GLOBAL_CFG);
>> - RdReg |= DCDC_GLOBAL_CFG_ENABLE_SRFLX;
>> - ret |= t2_out(PM_RECEIVER, RdReg, R_DCDC_GLOBAL_CFG);
>> + ret = twl4030_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &RdReg,
>> + R_DCDC_GLOBAL_CFG);
>>
>> + RdReg |= DCDC_GLOBAL_CFG_ENABLE_SRFLX;
>> + ret |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, RdReg,
>> + R_DCDC_GLOBAL_CFG);
>>
>> printk(KERN_INFO "SmartReflex driver initialized\n");
>>
>> - ret = subsys_create_file(&power_subsys, &sr_vdd1_autocomp);
>> + ret = sysfs_create_file(power_kobj, &sr_vdd1_autocomp.attr);
>> if (ret)
>> - printk(KERN_ERR "subsys_create_file failed: %d\n", ret);
>> + printk(KERN_ERR "sysfs_create_file failed: %d\n", ret);
>>
>> - ret = subsys_create_file(&power_subsys, &sr_vdd2_autocomp);
>> + ret = sysfs_create_file(power_kobj, &sr_vdd2_autocomp.attr);
>> if (ret)
>> - printk(KERN_ERR "subsys_create_file failed: %d\n", ret);
>> + printk(KERN_ERR "sysfs_create_file failed: %d\n", ret);
>>
>> return 0;
>> }
>>
>> -arch_initcall(omap3_sr_init);
>> +late_initcall(omap3_sr_init);
>> --
>> 1.5.4.3
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
>> the body of a message to ***@vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>>
>
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Kalle Jokiniemi
2008-05-30 14:12:25 UTC
Permalink
The following patch set integrates TI's SmartReflex driver. SmartReflex is a
module that adjusts OMAP3 VDD1 and VDD2 operating voltages around the nominal
values of current operating point depending on silicon characteristics and
operating conditions.

The driver creates two sysfs entries into /sys/power/ named "sr_vdd1_autocomp"
and "sr_vdd2_autocomp" which can be used to activate SmartReflex modules 1 and
2.

Use the following commands to enable SmartReflex:

echo -n 1 > /sys/power/sr_vdd1_autocomp
echo -n 1 > /sys/power/sr_vdd2_autocomp

To disable:

echo -n 0 > /sys/power/sr_vdd1_autocomp
echo -n 0 > /sys/power/sr_vdd2_autocomp

This particular patch adds the TI reference source and header files for
SmartReflex. Only modifications include minor styling to pass checkpatch.pl
test.


Signed-off-by: Kalle Jokiniemi <ext-***@nokia.com>
---
arch/arm/mach-omap2/smartreflex.c | 815 +++++++++++++++++++++++++++++++++++++
arch/arm/mach-omap2/smartreflex.h | 136 ++++++
2 files changed, 951 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/smartreflex.c
create mode 100644 arch/arm/mach-omap2/smartreflex.h

diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
new file mode 100644
index 0000000..dae7460
--- /dev/null
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -0,0 +1,815 @@
+/*
+ * linux/arch/arm/mach-omap3/smartreflex.c
+ *
+ * OMAP34XX SmartReflex Voltage Control
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Lesly A M <***@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/sysfs.h>
+
+#include <asm/arch/prcm.h>
+#include <asm/arch/power_companion.h>
+#include <linux/io.h>
+
+#include "prcm-regs.h"
+#include "smartreflex.h"
+
+
+/* #define DEBUG_SR 1 */
+#ifdef DEBUG_SR
+# define DPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__ ,\
+ ## args)
+#else
+# define DPRINTK(fmt, args...)
+#endif
+
+struct omap_sr{
+ int srid;
+ int is_sr_reset;
+ int is_autocomp_active;
+ struct clk *fck;
+ u32 req_opp_no;
+ u32 opp1_nvalue, opp2_nvalue, opp3_nvalue, opp4_nvalue, opp5_nvalue;
+ u32 senp_mod, senn_mod;
+ u32 srbase_addr;
+ u32 vpbase_addr;
+};
+
+static struct omap_sr sr1 = {
+ .srid = SR1,
+ .is_sr_reset = 1,
+ .is_autocomp_active = 0,
+ .srbase_addr = OMAP34XX_SR1_BASE,
+};
+
+static struct omap_sr sr2 = {
+ .srid = SR2,
+ .is_sr_reset = 1,
+ .is_autocomp_active = 0,
+ .srbase_addr = OMAP34XX_SR2_BASE,
+};
+
+static inline void sr_write_reg(struct omap_sr *sr, int offset, u32 value)
+{
+ omap_writel(value, sr->srbase_addr + offset);
+}
+
+static inline void sr_modify_reg(struct omap_sr *sr, int offset, u32 mask,
+ u32 value)
+{
+ u32 reg_val;
+
+ reg_val = omap_readl(sr->srbase_addr + offset);
+ reg_val &= ~mask;
+ reg_val |= value;
+
+ omap_writel(reg_val, sr->srbase_addr + offset);
+}
+
+static inline u32 sr_read_reg(struct omap_sr *sr, int offset)
+{
+ return omap_readl(sr->srbase_addr + offset);
+}
+
+
+#ifndef USE_EFUSE_VALUES
+static void cal_reciprocal(u32 sensor, u32 *sengain, u32 *rnsen)
+{
+ u32 gn, rn, mul;
+
+ for (gn = 0; gn < GAIN_MAXLIMIT; gn++) {
+ mul = 1 << (gn + 8);
+ rn = mul / sensor;
+ if (rn < R_MAXLIMIT) {
+ *sengain = gn;
+ *rnsen = rn;
+ }
+ }
+}
+#endif
+
+static int sr_clk_enable(struct omap_sr *sr)
+{
+ if (clk_enable(sr->fck) != 0) {
+ printk(KERN_ERR "Could not enable sr%d_fck\n", sr->srid);
+ goto clk_enable_err;
+ }
+
+ /* set fclk- active , iclk- idle */
+ sr_modify_reg(sr, ERRCONFIG, SR_CLKACTIVITY_MASK,
+ SR_CLKACTIVITY_IOFF_FON);
+
+ return 0;
+
+clk_enable_err:
+ return -1;
+}
+
+static int sr_clk_disable(struct omap_sr *sr)
+{
+ /* set fclk, iclk- idle */
+ sr_modify_reg(sr, ERRCONFIG, SR_CLKACTIVITY_MASK,
+ SR_CLKACTIVITY_IOFF_FOFF);
+
+ clk_disable(sr->fck);
+ sr->is_sr_reset = 1;
+
+ return 0;
+}
+
+static void sr_set_nvalues(struct omap_sr *sr)
+{
+#ifdef USE_EFUSE_VALUES
+ u32 n1, n2;
+#else
+ u32 senpval, sennval;
+ u32 senpgain, senngain;
+ u32 rnsenp, rnsenn;
+#endif
+
+ if (sr->srid == SR1) {
+#ifdef USE_EFUSE_VALUES
+ /* Read values for VDD1 from EFUSE */
+#else
+ /* since E-Fuse Values are not available, calculating the
+ * reciprocal of the SenN and SenP values for SR1
+ */
+ sr->senp_mod = 0x03; /* SenN-M5 enabled */
+ sr->senn_mod = 0x03;
+
+ /* for OPP5 */
+ senpval = 0x848 + 0x330;
+ sennval = 0xacd + 0x330;
+
+ cal_reciprocal(senpval, &senpgain, &rnsenp);
+ cal_reciprocal(sennval, &senngain, &rnsenn);
+
+ sr->opp5_nvalue =
+ ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
+ (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
+ (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
+ (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
+
+ /* for OPP4 */
+ senpval = 0x727 + 0x2a0;
+ sennval = 0x964 + 0x2a0;
+
+ cal_reciprocal(senpval, &senpgain, &rnsenp);
+ cal_reciprocal(sennval, &senngain, &rnsenn);
+
+ sr->opp4_nvalue =
+ ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
+ (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
+ (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
+ (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
+
+ /* for OPP3 */
+ senpval = 0x655 + 0x200;
+ sennval = 0x85b + 0x200;
+
+ cal_reciprocal(senpval, &senpgain, &rnsenp);
+ cal_reciprocal(sennval, &senngain, &rnsenn);
+
+ sr->opp3_nvalue =
+ ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
+ (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
+ (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
+ (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
+
+ /* for OPP2 */
+ senpval = 0x3be + 0x1a0;
+ sennval = 0x506 + 0x1a0;
+
+ cal_reciprocal(senpval, &senpgain, &rnsenp);
+ cal_reciprocal(sennval, &senngain, &rnsenn);
+
+ sr->opp2_nvalue =
+ ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
+ (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
+ (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
+ (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
+
+ /* for OPP1 */
+ senpval = 0x28c + 0x100;
+ sennval = 0x373 + 0x100;
+
+ cal_reciprocal(senpval, &senpgain, &rnsenp);
+ cal_reciprocal(sennval, &senngain, &rnsenn);
+
+ sr->opp1_nvalue =
+ ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
+ (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
+ (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
+ (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
+
+ sr_clk_enable(sr);
+ sr_write_reg(sr, NVALUERECIPROCAL, sr->opp3_nvalue);
+ sr_clk_disable(sr);
+
+#endif
+ } else if (sr->srid == SR2) {
+#ifdef USE_EFUSE_VALUES
+ /* Read values for VDD2 from EFUSE */
+#else
+ /* since E-Fuse Values are not available, calculating the
+ * reciprocal of the SenN and SenP values for SR2
+ */
+ sr->senp_mod = 0x03;
+ sr->senn_mod = 0x03;
+
+ /* for OPP3 */
+ senpval = 0x579 + 0x200;
+ sennval = 0x76f + 0x200;
+
+ cal_reciprocal(senpval, &senpgain, &rnsenp);
+ cal_reciprocal(sennval, &senngain, &rnsenn);
+
+ sr->opp3_nvalue =
+ ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
+ (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
+ (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
+ (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
+
+ /* for OPP2 */
+ senpval = 0x390 + 0x1c0;
+ sennval = 0x4f5 + 0x1c0;
+
+ cal_reciprocal(senpval, &senpgain, &rnsenp);
+ cal_reciprocal(sennval, &senngain, &rnsenn);
+
+ sr->opp2_nvalue =
+ ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
+ (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
+ (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
+ (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
+
+ /* for OPP1 */
+ senpval = 0x25d;
+ sennval = 0x359;
+
+ cal_reciprocal(senpval, &senpgain, &rnsenp);
+ cal_reciprocal(sennval, &senngain, &rnsenn);
+
+ sr->opp1_nvalue =
+ ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
+ (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
+ (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
+ (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
+
+#endif
+ }
+
+}
+
+static void sr_configure_vp(int srid)
+{
+ u32 vpconfig;
+
+ if (srid == SR1) {
+ vpconfig = PRM_VP1_CONFIG_ERROROFFSET | PRM_VP1_CONFIG_ERRORGAIN
+ | PRM_VP1_CONFIG_INITVOLTAGE | PRM_VP1_CONFIG_TIMEOUTEN;
+
+ PRM_VP1_CONFIG = vpconfig;
+ PRM_VP1_VSTEPMIN = PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN |
+ PRM_VP1_VSTEPMIN_VSTEPMIN;
+
+ PRM_VP1_VSTEPMAX = PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX |
+ PRM_VP1_VSTEPMAX_VSTEPMAX;
+
+ PRM_VP1_VLIMITTO = PRM_VP1_VLIMITTO_VDDMAX |
+ PRM_VP1_VLIMITTO_VDDMIN | PRM_VP1_VLIMITTO_TIMEOUT;
+
+ PRM_VP1_CONFIG |= PRM_VP1_CONFIG_INITVDD;
+ PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_INITVDD;
+
+ } else if (srid == SR2) {
+ vpconfig = PRM_VP2_CONFIG_ERROROFFSET | PRM_VP2_CONFIG_ERRORGAIN
+ | PRM_VP2_CONFIG_INITVOLTAGE | PRM_VP2_CONFIG_TIMEOUTEN;
+
+ PRM_VP2_CONFIG = vpconfig;
+ PRM_VP2_VSTEPMIN = PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN |
+ PRM_VP2_VSTEPMIN_VSTEPMIN;
+
+ PRM_VP2_VSTEPMAX = PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX |
+ PRM_VP2_VSTEPMAX_VSTEPMAX;
+
+ PRM_VP2_VLIMITTO = PRM_VP2_VLIMITTO_VDDMAX |
+ PRM_VP2_VLIMITTO_VDDMIN | PRM_VP2_VLIMITTO_TIMEOUT;
+
+ PRM_VP2_CONFIG |= PRM_VP2_CONFIG_INITVDD;
+ PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_INITVDD;
+
+ }
+}
+
+static void sr_configure_vc(void)
+{
+ PRM_VC_SMPS_SA =
+ (R_SRI2C_SLAVE_ADDR << PRM_VC_SMPS_SA1_SHIFT) |
+ (R_SRI2C_SLAVE_ADDR << PRM_VC_SMPS_SA0_SHIFT);
+
+ PRM_VC_SMPS_VOL_RA = (R_VDD2_SR_CONTROL << PRM_VC_SMPS_VOLRA1_SHIFT) |
+ (R_VDD1_SR_CONTROL << PRM_VC_SMPS_VOLRA0_SHIFT);
+
+ PRM_VC_CMD_VAL_0 = (PRM_VC_CMD_VAL0_ON << PRM_VC_CMD_ON_SHIFT) |
+ (PRM_VC_CMD_VAL0_ONLP << PRM_VC_CMD_ONLP_SHIFT) |
+ (PRM_VC_CMD_VAL0_RET << PRM_VC_CMD_RET_SHIFT) |
+ (PRM_VC_CMD_VAL0_OFF << PRM_VC_CMD_OFF_SHIFT);
+
+ PRM_VC_CMD_VAL_1 = (PRM_VC_CMD_VAL1_ON << PRM_VC_CMD_ON_SHIFT) |
+ (PRM_VC_CMD_VAL1_ONLP << PRM_VC_CMD_ONLP_SHIFT) |
+ (PRM_VC_CMD_VAL1_RET << PRM_VC_CMD_RET_SHIFT) |
+ (PRM_VC_CMD_VAL1_OFF << PRM_VC_CMD_OFF_SHIFT);
+
+ PRM_VC_CH_CONF = PRM_VC_CH_CONF_CMD1 | PRM_VC_CH_CONF_RAV1;
+
+ PRM_VC_I2C_CFG = PRM_VC_I2C_CFG_MCODE | PRM_VC_I2C_CFG_HSEN
+ | PRM_VC_I2C_CFG_SREN;
+
+ /* Setup voltctrl and other setup times */
+#ifdef CONFIG_SYSOFFMODE
+ PRM_VOLTCTRL = PRM_VOLTCTRL_AUTO_OFF | PRM_VOLTCTRL_AUTO_RET;
+ PRM_CLKSETUP = PRM_CLKSETUP_DURATION;
+ PRM_VOLTSETUP1 = (PRM_VOLTSETUP_TIME2 << PRM_VOLTSETUP_TIME2_OFFSET) |
+ (PRM_VOLTSETUP_TIME1 << PRM_VOLTSETUP_TIME1_OFFSET);
+ PRM_VOLTOFFSET = PRM_VOLTOFFSET_DURATION;
+ PRM_VOLTSETUP2 = PRM_VOLTSETUP2_DURATION;
+#else
+ PRM_VOLTCTRL |= PRM_VOLTCTRL_AUTO_RET;
+#endif
+
+}
+
+
+static void sr_configure(struct omap_sr *sr)
+{
+ u32 sys_clk, sr_clk_length = 0;
+ u32 sr_config;
+ u32 senp_en , senn_en;
+
+ senp_en = sr->senp_mod;
+ senn_en = sr->senn_mod;
+
+ sys_clk = prcm_get_system_clock_speed();
+
+ switch (sys_clk) {
+ case 12000:
+ sr_clk_length = SRCLKLENGTH_12MHZ_SYSCLK;
+ break;
+ case 13000:
+ sr_clk_length = SRCLKLENGTH_13MHZ_SYSCLK;
+ break;
+ case 19200:
+ sr_clk_length = SRCLKLENGTH_19MHZ_SYSCLK;
+ break;
+ case 26000:
+ sr_clk_length = SRCLKLENGTH_26MHZ_SYSCLK;
+ break;
+ case 38400:
+ sr_clk_length = SRCLKLENGTH_38MHZ_SYSCLK;
+ break;
+ default :
+ printk(KERN_ERR "Invalid sysclk value\n");
+ break;
+ }
+
+ DPRINTK(KERN_DEBUG "SR : sys clk %lu\n", sys_clk);
+ if (sr->srid == SR1) {
+ sr_config = SR1_SRCONFIG_ACCUMDATA |
+ (sr_clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
+ SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN |
+ SRCONFIG_MINMAXAVG_EN |
+ (senn_en << SRCONFIG_SENNENABLE_SHIFT) |
+ (senp_en << SRCONFIG_SENPENABLE_SHIFT) |
+ SRCONFIG_DELAYCTRL;
+
+ sr_write_reg(sr, SRCONFIG, sr_config);
+
+ sr_write_reg(sr, AVGWEIGHT, SR1_AVGWEIGHT_SENPAVGWEIGHT |
+ SR1_AVGWEIGHT_SENNAVGWEIGHT);
+
+ sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK |
+ SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
+ (SR1_ERRWEIGHT | SR1_ERRMAXLIMIT | SR1_ERRMINLIMIT));
+
+ } else if (sr->srid == SR2) {
+ sr_config = SR2_SRCONFIG_ACCUMDATA |
+ (sr_clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
+ SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN |
+ SRCONFIG_MINMAXAVG_EN |
+ (senn_en << SRCONFIG_SENNENABLE_SHIFT) |
+ (senp_en << SRCONFIG_SENPENABLE_SHIFT) |
+ SRCONFIG_DELAYCTRL;
+
+ sr_write_reg(sr, SRCONFIG, sr_config);
+
+ sr_write_reg(sr, AVGWEIGHT, SR2_AVGWEIGHT_SENPAVGWEIGHT |
+ SR2_AVGWEIGHT_SENNAVGWEIGHT);
+
+ sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK |
+ SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
+ (SR2_ERRWEIGHT | SR2_ERRMAXLIMIT | SR2_ERRMINLIMIT));
+
+ }
+ sr->is_sr_reset = 0;
+}
+
+static void sr_enable(struct omap_sr *sr, u32 target_opp_no)
+{
+ u32 nvalue_reciprocal, current_nvalue;
+
+ sr->req_opp_no = target_opp_no;
+
+ if (sr->srid == SR1) {
+ switch (target_opp_no) {
+ case 5:
+ nvalue_reciprocal = sr->opp5_nvalue;
+ break;
+ case 4:
+ nvalue_reciprocal = sr->opp4_nvalue;
+ break;
+ case 3:
+ nvalue_reciprocal = sr->opp3_nvalue;
+ break;
+ case 2:
+ nvalue_reciprocal = sr->opp2_nvalue;
+ break;
+ case 1:
+ nvalue_reciprocal = sr->opp1_nvalue;
+ break;
+ default:
+ nvalue_reciprocal = sr->opp3_nvalue;
+ break;
+ }
+ } else {
+ switch (target_opp_no) {
+ case 3:
+ nvalue_reciprocal = sr->opp3_nvalue;
+ break;
+ case 2:
+ nvalue_reciprocal = sr->opp2_nvalue;
+ break;
+ case 1:
+ nvalue_reciprocal = sr->opp1_nvalue;
+ break;
+ default:
+ nvalue_reciprocal = sr->opp3_nvalue;
+ break;
+ }
+ }
+
+ current_nvalue = sr_read_reg(sr, NVALUERECIPROCAL);
+
+ if (current_nvalue == nvalue_reciprocal) {
+ DPRINTK("System is already at the desired voltage level\n");
+ return;
+ }
+
+ sr_write_reg(sr, NVALUERECIPROCAL, nvalue_reciprocal);
+
+ /* Enable the interrupt */
+ sr_modify_reg(sr, ERRCONFIG,
+ (ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST),
+ (ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST));
+
+ if (sr->srid == SR1) {
+ /* Enable VP1 */
+ PRM_VP1_CONFIG |= PRM_VP1_CONFIG_VPENABLE;
+ } else if (sr->srid == SR2) {
+ /* Enable VP2 */
+ PRM_VP2_CONFIG |= PRM_VP2_CONFIG_VPENABLE;
+ }
+
+ /* SRCONFIG - enable SR */
+ sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE);
+
+}
+
+static void sr_disable(struct omap_sr *sr)
+{
+ sr->is_sr_reset = 1;
+
+ /* SRCONFIG - disable SR */
+ sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, ~SRCONFIG_SRENABLE);
+
+ if (sr->srid == SR1) {
+ /* Enable VP1 */
+ PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_VPENABLE;
+ } else if (sr->srid == SR2) {
+ /* Enable VP2 */
+ PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_VPENABLE;
+ }
+}
+
+
+void sr_start_vddautocomap(int srid, u32 target_opp_no)
+{
+ struct omap_sr *sr = NULL;
+
+ if (srid == SR1)
+ sr = &sr1;
+ else if (srid == SR2)
+ sr = &sr2;
+
+ if (sr->is_sr_reset == 1) {
+ sr_clk_enable(sr);
+ sr_configure(sr);
+ }
+
+ if (sr->is_autocomp_active == 1)
+ DPRINTK(KERN_WARNING "SR%d: VDD autocomp is already active\n",
+ srid);
+
+ sr->is_autocomp_active = 1;
+ sr_enable(sr, target_opp_no);
+}
+EXPORT_SYMBOL(sr_start_vddautocomap);
+
+int sr_stop_vddautocomap(int srid)
+{
+ struct omap_sr *sr = NULL;
+
+ if (srid == SR1)
+ sr = &sr1;
+ else if (srid == SR2)
+ sr = &sr2;
+
+ if (sr->is_autocomp_active == 1) {
+ sr_disable(sr);
+ sr_clk_disable(sr);
+ sr->is_autocomp_active = 0;
+ return SR_TRUE;
+ } else {
+ DPRINTK(KERN_WARNING "SR%d: VDD autocomp is not active\n",
+ srid);
+ return SR_FALSE;
+ }
+
+}
+EXPORT_SYMBOL(sr_stop_vddautocomap);
+
+void enable_smartreflex(int srid)
+{
+ u32 target_opp_no = 0;
+ struct omap_sr *sr = NULL;
+
+ if (srid == SR1)
+ sr = &sr1;
+ else if (srid == SR2)
+ sr = &sr2;
+
+ if (sr->is_autocomp_active == 1) {
+ if (sr->is_sr_reset == 1) {
+ if (srid == SR1) {
+ /* Enable SR clks */
+ CM_FCLKEN_WKUP |= SR1_CLK_ENABLE;
+ target_opp_no = get_opp_no(current_vdd1_opp);
+
+ } else if (srid == SR2) {
+ /* Enable SR clks */
+ CM_FCLKEN_WKUP |= SR2_CLK_ENABLE;
+ target_opp_no = get_opp_no(current_vdd2_opp);
+ }
+
+ sr_configure(sr);
+
+ sr_enable(sr, target_opp_no);
+ }
+ }
+}
+
+void disable_smartreflex(int srid)
+{
+ struct omap_sr *sr = NULL;
+
+ if (srid == SR1)
+ sr = &sr1;
+ else if (srid == SR2)
+ sr = &sr2;
+
+ if (sr->is_autocomp_active == 1) {
+ if (srid == SR1) {
+ /* Enable SR clk */
+ CM_FCLKEN_WKUP |= SR1_CLK_ENABLE;
+
+ } else if (srid == SR2) {
+ /* Enable SR clk */
+ CM_FCLKEN_WKUP |= SR2_CLK_ENABLE;
+ }
+
+ if (sr->is_sr_reset == 0) {
+
+ sr->is_sr_reset = 1;
+ /* SRCONFIG - disable SR */
+ sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE,
+ ~SRCONFIG_SRENABLE);
+
+ if (sr->srid == SR1) {
+ /* Disable SR clk */
+ CM_FCLKEN_WKUP &= ~SR1_CLK_ENABLE;
+ /* Enable VP1 */
+ PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_VPENABLE;
+
+ } else if (sr->srid == SR2) {
+ /* Disable SR clk */
+ CM_FCLKEN_WKUP &= ~SR2_CLK_ENABLE;
+ /* Enable VP2 */
+ PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_VPENABLE;
+ }
+ }
+ }
+}
+
+
+/* Voltage Scaling using SR VCBYPASS */
+int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel)
+{
+ int ret;
+ int sr_status = 0;
+ u32 vdd, target_opp_no;
+ u32 vc_bypass_value;
+ u32 reg_addr = 0;
+ u32 loop_cnt = 0, retries_cnt = 0;
+
+ vdd = get_vdd(target_opp);
+ target_opp_no = get_opp_no(target_opp);
+
+ if (vdd == PRCM_VDD1) {
+ sr_status = sr_stop_vddautocomap(SR1);
+
+ PRM_VC_CMD_VAL_0 = (PRM_VC_CMD_VAL_0 & ~PRM_VC_CMD_ON_MASK) |
+ (vsel << PRM_VC_CMD_ON_SHIFT);
+ reg_addr = R_VDD1_SR_CONTROL;
+
+ } else if (vdd == PRCM_VDD2) {
+ sr_status = sr_stop_vddautocomap(SR2);
+
+ PRM_VC_CMD_VAL_1 = (PRM_VC_CMD_VAL_1 & ~PRM_VC_CMD_ON_MASK) |
+ (vsel << PRM_VC_CMD_ON_SHIFT);
+ reg_addr = R_VDD2_SR_CONTROL;
+ }
+
+ vc_bypass_value = (vsel << PRM_VC_BYPASS_DATA_SHIFT) |
+ (reg_addr << PRM_VC_BYPASS_REGADDR_SHIFT) |
+ (R_SRI2C_SLAVE_ADDR << PRM_VC_BYPASS_SLAVEADDR_SHIFT);
+
+ PRM_VC_BYPASS_VAL = vc_bypass_value;
+
+ PRM_VC_BYPASS_VAL |= PRM_VC_BYPASS_VALID;
+
+ DPRINTK("%s : PRM_VC_BYPASS_VAL %X\n", __func__, PRM_VC_BYPASS_VAL);
+ DPRINTK("PRM_IRQST_MPU %X\n", PRM_IRQSTATUS_MPU);
+
+ while ((PRM_VC_BYPASS_VAL & PRM_VC_BYPASS_VALID) != 0x0) {
+ ret = loop_wait(&loop_cnt, &retries_cnt, 10);
+ if (ret != PRCM_PASS) {
+ printk(KERN_INFO "Loop count exceeded in check SR I2C"
+ "write\n");
+ return ret;
+ }
+ }
+
+ omap_udelay(T2_SMPS_UPDATE_DELAY);
+
+ if (sr_status) {
+ if (vdd == PRCM_VDD1)
+ sr_start_vddautocomap(SR1, target_opp_no);
+ else if (vdd == PRCM_VDD2)
+ sr_start_vddautocomap(SR2, target_opp_no);
+ }
+
+ return SR_PASS;
+}
+
+/* Sysfs interface to select SR VDD1 auto compensation */
+static ssize_t omap_sr_vdd1_autocomp_show(struct kset *subsys, char *buf)
+{
+ return sprintf(buf, "%d\n", sr1.is_autocomp_active);
+}
+
+static ssize_t omap_sr_vdd1_autocomp_store(struct kset *subsys,
+ const char *buf, size_t n)
+{
+ u32 current_vdd1opp_no;
+ unsigned short value;
+
+ if (sscanf(buf, "%hu", &value) != 1 || (value > 1)) {
+ printk(KERN_ERR "sr_vdd1_autocomp: Invalid value\n");
+ return -EINVAL;
+ }
+
+ current_vdd1opp_no = get_opp_no(current_vdd1_opp);
+
+ if (value == 0)
+ sr_stop_vddautocomap(SR1);
+ else
+ sr_start_vddautocomap(SR1, current_vdd1opp_no);
+
+ return n;
+}
+
+static struct subsys_attribute sr_vdd1_autocomp = {
+ .attr = {
+ .name = __stringify(sr_vdd1_autocomp),
+ .mode = 0644,
+ },
+ .show = omap_sr_vdd1_autocomp_show,
+ .store = omap_sr_vdd1_autocomp_store,
+};
+
+/* Sysfs interface to select SR VDD2 auto compensation */
+static ssize_t omap_sr_vdd2_autocomp_show(struct kset *subsys, char *buf)
+{
+ return sprintf(buf, "%d\n", sr2.is_autocomp_active);
+}
+
+static ssize_t omap_sr_vdd2_autocomp_store(struct kset *subsys,
+ const char *buf, size_t n)
+{
+ u32 current_vdd2opp_no;
+ unsigned short value;
+
+ if (sscanf(buf, "%hu", &value) != 1 || (value > 1)) {
+ printk(KERN_ERR "sr_vdd2_autocomp: Invalid value\n");
+ return -EINVAL;
+ }
+
+ current_vdd2opp_no = get_opp_no(current_vdd2_opp);
+
+ if (value == 0)
+ sr_stop_vddautocomap(SR2);
+ else
+ sr_start_vddautocomap(SR2, current_vdd2opp_no);
+
+ return n;
+}
+
+static struct subsys_attribute sr_vdd2_autocomp = {
+ .attr = {
+ .name = __stringify(sr_vdd2_autocomp),
+ .mode = 0644,
+ },
+ .show = omap_sr_vdd2_autocomp_show,
+ .store = omap_sr_vdd2_autocomp_store,
+};
+
+
+
+static int __init omap3_sr_init(void)
+{
+ int ret = 0;
+ u8 RdReg;
+
+#ifdef CONFIG_ARCH_OMAP34XX
+ sr1.fck = clk_get(NULL, "sr1_fck");
+ if (IS_ERR(sr1.fck))
+ printk(KERN_ERR "Could not get sr1_fck\n");
+
+ sr2.fck = clk_get(NULL, "sr2_fck");
+ if (IS_ERR(sr2.fck))
+ printk(KERN_ERR "Could not get sr2_fck\n");
+#endif /* #ifdef CONFIG_ARCH_OMAP34XX */
+
+ /* Call the VPConfig, VCConfig, set N Values. */
+ sr_set_nvalues(&sr1);
+ sr_configure_vp(SR1);
+
+ sr_set_nvalues(&sr2);
+ sr_configure_vp(SR2);
+
+ sr_configure_vc();
+
+ /* Enable SR on T2 */
+ ret = t2_in(PM_RECEIVER, &RdReg, R_DCDC_GLOBAL_CFG);
+ RdReg |= DCDC_GLOBAL_CFG_ENABLE_SRFLX;
+ ret |= t2_out(PM_RECEIVER, RdReg, R_DCDC_GLOBAL_CFG);
+
+
+ printk(KERN_INFO "SmartReflex driver initialized\n");
+
+ ret = subsys_create_file(&power_subsys, &sr_vdd1_autocomp);
+ if (ret)
+ printk(KERN_ERR "subsys_create_file failed: %d\n", ret);
+
+ ret = subsys_create_file(&power_subsys, &sr_vdd2_autocomp);
+ if (ret)
+ printk(KERN_ERR "subsys_create_file failed: %d\n", ret);
+
+ return 0;
+}
+
+arch_initcall(omap3_sr_init);
diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
new file mode 100644
index 0000000..62907ef
--- /dev/null
+++ b/arch/arm/mach-omap2/smartreflex.h
@@ -0,0 +1,136 @@
+/*
+ * linux/arch/arm/mach-omap3/smartreflex.h
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Lesly A M <***@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+
+/* SR Modules */
+#define SR1 1
+#define SR2 2
+
+#define SR_FAIL 1
+#define SR_PASS 0
+
+#define SR_TRUE 1
+#define SR_FALSE 0
+
+#define GAIN_MAXLIMIT 16
+#define R_MAXLIMIT 256
+
+#define SR1_CLK_ENABLE (0x1 << 6)
+#define SR2_CLK_ENABLE (0x1 << 7)
+
+/* PRM_VP1_CONFIG */
+#define PRM_VP1_CONFIG_ERROROFFSET (0x00 << 24)
+#define PRM_VP1_CONFIG_ERRORGAIN (0x20 << 16)
+
+#define PRM_VP1_CONFIG_INITVOLTAGE (0x30 << 8) /* 1.2 volt */
+#define PRM_VP1_CONFIG_TIMEOUTEN (0x1 << 3)
+#define PRM_VP1_CONFIG_INITVDD (0x1 << 2)
+#define PRM_VP1_CONFIG_FORCEUPDATE (0x1 << 1)
+#define PRM_VP1_CONFIG_VPENABLE (0x1 << 0)
+
+/* PRM_VP1_VSTEPMIN */
+#define PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN (0x01F4 << 8)
+#define PRM_VP1_VSTEPMIN_VSTEPMIN (0x01 << 0)
+
+/* PRM_VP1_VSTEPMAX */
+#define PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX (0x01F4 << 8)
+#define PRM_VP1_VSTEPMAX_VSTEPMAX (0x04 << 0)
+
+/* PRM_VP1_VLIMITTO */
+#define PRM_VP1_VLIMITTO_VDDMAX (0x3C << 24)
+#define PRM_VP1_VLIMITTO_VDDMIN (0x0 << 16)
+#define PRM_VP1_VLIMITTO_TIMEOUT (0xFFFF << 0)
+
+/* PRM_VP2_CONFIG */
+#define PRM_VP2_CONFIG_ERROROFFSET (0x00 << 24)
+#define PRM_VP2_CONFIG_ERRORGAIN (0x20 << 16)
+
+#define PRM_VP2_CONFIG_INITVOLTAGE (0x30 << 8) /* 1.2 volt */
+#define PRM_VP2_CONFIG_TIMEOUTEN (0x1 << 3)
+#define PRM_VP2_CONFIG_INITVDD (0x1 << 2)
+#define PRM_VP2_CONFIG_FORCEUPDATE (0x1 << 1)
+#define PRM_VP2_CONFIG_VPENABLE (0x1 << 0)
+
+/* PRM_VP2_VSTEPMIN */
+#define PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN (0x01F4 << 8)
+#define PRM_VP2_VSTEPMIN_VSTEPMIN (0x01 << 0)
+
+/* PRM_VP2_VSTEPMAX */
+#define PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX (0x01F4 << 8)
+#define PRM_VP2_VSTEPMAX_VSTEPMAX (0x04 << 0)
+
+/* PRM_VP2_VLIMITTO */
+#define PRM_VP2_VLIMITTO_VDDMAX (0x2C << 24)
+#define PRM_VP2_VLIMITTO_VDDMIN (0x0 << 16)
+#define PRM_VP2_VLIMITTO_TIMEOUT (0xFFFF << 0)
+
+/* SRCONFIG */
+#define SR1_SRCONFIG_ACCUMDATA (0x1F4 << 22)
+#define SR2_SRCONFIG_ACCUMDATA (0x1F4 << 22)
+
+#define SRCLKLENGTH_12MHZ_SYSCLK 0x3C
+#define SRCLKLENGTH_13MHZ_SYSCLK 0x41
+#define SRCLKLENGTH_19MHZ_SYSCLK 0x60
+#define SRCLKLENGTH_26MHZ_SYSCLK 0x82
+#define SRCLKLENGTH_38MHZ_SYSCLK 0xC0
+
+#define SRCONFIG_SRCLKLENGTH_SHIFT 12
+#define SRCONFIG_SENNENABLE_SHIFT 5
+#define SRCONFIG_SENPENABLE_SHIFT 3
+
+#define SRCONFIG_SRENABLE (0x01 << 11)
+#define SRCONFIG_SENENABLE (0x01 << 10)
+#define SRCONFIG_ERRGEN_EN (0x01 << 9)
+#define SRCONFIG_MINMAXAVG_EN (0x01 << 8)
+
+#define SRCONFIG_DELAYCTRL (0x01 << 2)
+#define SRCONFIG_CLKCTRL (0x00 << 0)
+
+/* AVGWEIGHT */
+#define SR1_AVGWEIGHT_SENPAVGWEIGHT (0x03 << 2)
+#define SR1_AVGWEIGHT_SENNAVGWEIGHT (0x03 << 0)
+
+#define SR2_AVGWEIGHT_SENPAVGWEIGHT (0x01 << 2)
+#define SR2_AVGWEIGHT_SENNAVGWEIGHT (0x01 << 0)
+
+/* NVALUERECIPROCAL */
+#define NVALUERECIPROCAL_SENPGAIN_SHIFT 20
+#define NVALUERECIPROCAL_SENNGAIN_SHIFT 16
+#define NVALUERECIPROCAL_RNSENP_SHIFT 8
+#define NVALUERECIPROCAL_RNSENN_SHIFT 0
+
+/* ERRCONFIG */
+#define SR_CLKACTIVITY_MASK (0x03 << 20)
+#define SR_ERRWEIGHT_MASK (0x07 << 16)
+#define SR_ERRMAXLIMIT_MASK (0xFF << 8)
+#define SR_ERRMINLIMIT_MASK (0xFF << 0)
+
+#define SR_CLKACTIVITY_IOFF_FOFF (0x00 << 20)
+#define SR_CLKACTIVITY_IOFF_FON (0x02 << 20)
+
+#define ERRCONFIG_VPBOUNDINTEN (0x1 << 31)
+#define ERRCONFIG_VPBOUNDINTST (0x1 << 30)
+
+#define SR1_ERRWEIGHT (0x07 << 16)
+#define SR1_ERRMAXLIMIT (0x02 << 8)
+#define SR1_ERRMINLIMIT (0xFA << 0)
+
+#define SR2_ERRWEIGHT (0x07 << 16)
+#define SR2_ERRMAXLIMIT (0x02 << 8)
+#define SR2_ERRMINLIMIT (0xF9 << 0)
+
+extern u32 current_vdd1_opp;
+extern u32 current_vdd2_opp;
+extern struct kset power_subsys;
+
+extern inline int loop_wait(u32 *lcnt, u32 *rcnt, u32 delay);
+extern void omap_udelay(u32 udelay);
+
--
1.5.4.3

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Kalle Jokiniemi
2008-05-30 14:12:26 UTC
Permalink
Added new register and bit definitions to enable Smartreflex driver integration.
Also PRM_VC_SMPS_SA bit definitions' naming was changed to match the naming of
other similar bit definitions.


Signed-off-by: Kalle Jokiniemi <ext-***@nokia.com>
---
arch/arm/mach-omap2/prm-regbits-34xx.h | 27 ++++++--
arch/arm/mach-omap2/smartreflex.h | 124 ++++++++++++++++++++++++++++++-
include/asm-arm/arch-omap/omap34xx.h | 2 +
3 files changed, 144 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index c6a7940..f82b5a7 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -435,10 +435,10 @@
/* PM_PWSTST_EMU specific bits */

/* PRM_VC_SMPS_SA */
-#define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT 16
-#define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16)
-#define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT 0
-#define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0)
+#define OMAP3430_SMPS_SA1_SHIFT 16
+#define OMAP3430_SMPS_SA1_MASK (0x7f << 16)
+#define OMAP3430_SMPS_SA0_SHIFT 0
+#define OMAP3430_SMPS_SA0_MASK (0x7f << 0)

/* PRM_VC_SMPS_VOL_RA */
#define OMAP3430_VOLRA1_SHIFT 16
@@ -452,7 +452,7 @@
#define OMAP3430_CMDRA0_SHIFT 0
#define OMAP3430_CMDRA0_MASK (0xff << 0)

-/* PRM_VC_CMD_VAL_0 specific bits */
+/* PRM_VC_CMD_VAL */
#define OMAP3430_VC_CMD_ON_SHIFT 24
#define OMAP3430_VC_CMD_ON_MASK (0xFF << 24)
#define OMAP3430_VC_CMD_ONLP_SHIFT 16
@@ -462,7 +462,17 @@
#define OMAP3430_VC_CMD_OFF_SHIFT 0
#define OMAP3430_VC_CMD_OFF_MASK (0xFF << 0)

+/* PRM_VC_CMD_VAL_0 specific bits */
+#define OMAP3430_VC_CMD_VAL0_ON (0x3 << 4)
+#define OMAP3430_VC_CMD_VAL0_ONLP (0x3 << 3)
+#define OMAP3430_VC_CMD_VAL0_RET (0x3 << 3)
+#define OMAP3430_VC_CMD_VAL0_OFF (0x3 << 3)
+
/* PRM_VC_CMD_VAL_1 specific bits */
+#define OMAP3430_VC_CMD_VAL1_ON (0xB << 2)
+#define OMAP3430_VC_CMD_VAL1_ONLP (0x3 << 3)
+#define OMAP3430_VC_CMD_VAL1_RET (0x3 << 3)
+#define OMAP3430_VC_CMD_VAL1_OFF (0x3 << 3)

/* PRM_VC_CH_CONF */
#define OMAP3430_CMD1 (1 << 20)
@@ -521,6 +531,13 @@
#define OMAP3430_AUTO_RET (1 << 1)
#define OMAP3430_AUTO_SLEEP (1 << 0)

+/* Constants to define setup durations */
+#define OMAP3430_CLKSETUP_DURATION 0xff
+#define OMAP3430_VOLTSETUP_TIME2 0xfff
+#define OMAP3430_VOLTSETUP_TIME1 0xfff
+#define OMAP3430_VOLTOFFSET_DURATION 0xff
+#define OMAP3430_VOLTSETUP2_DURATION 0xff
+
/* PRM_SRAM_PCHARGE */
#define OMAP3430_PCHARGE_TIME_SHIFT 0
#define OMAP3430_PCHARGE_TIME_MASK (0xff << 0)
diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
index 62907ef..2091a15 100644
--- a/arch/arm/mach-omap2/smartreflex.h
+++ b/arch/arm/mach-omap2/smartreflex.h
@@ -1,5 +1,10 @@
+#ifndef __ARCH_ARM_MACH_OMAP3_SMARTREFLEX_H
+#define __ARCH_ARM_MACH_OMAP3_SMARTREFLEX_H
/*
- * linux/arch/arm/mach-omap3/smartreflex.h
+ * linux/arch/arm/mach-omap2/smartreflex.h
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Kalle Jokiniemi
*
* Copyright (C) 2007 Texas Instruments, Inc.
* Lesly A M <***@ti.com>
@@ -9,6 +14,21 @@
* published by the Free Software Foundation.
*/

+#define PHY_TO_OFF_PM_MASTER(p) (p - 0x36)
+#define PHY_TO_OFF_PM_RECIEVER(p) (p - 0x5b)
+#define PHY_TO_OFF_PM_INT(p) (p - 0x2e)
+
+/* SMART REFLEX REG ADDRESS OFFSET */
+#define SRCONFIG 0x00
+#define SRSTATUS 0x04
+#define SENVAL 0x08
+#define SENMIN 0x0C
+#define SENMAX 0x10
+#define SENAVG 0x14
+#define AVGWEIGHT 0x18
+#define NVALUERECIPROCAL 0x1C
+#define SENERROR 0x20
+#define ERRCONFIG 0x24

/* SR Modules */
#define SR1 1
@@ -127,10 +147,106 @@
#define SR2_ERRMAXLIMIT (0x02 << 8)
#define SR2_ERRMINLIMIT (0xF9 << 0)

+/* T2 SMART REFLEX */
+#define R_SRI2C_SLAVE_ADDR 0x12
+#define R_VDD1_SR_CONTROL 0x00
+#define R_VDD2_SR_CONTROL 0x01
+#define T2_SMPS_UPDATE_DELAY 360 /* In uSec */
+
+/* Vmode control */
+#define R_DCDC_GLOBAL_CFG PHY_TO_OFF_PM_RECIEVER(0x61)
+
+#define R_VDD1_VSEL PHY_TO_OFF_PM_RECIEVER(0xb9)
+#define R_VDD1_VMODE_CFG PHY_TO_OFF_PM_RECIEVER(0xba)
+#define R_VDD1_VFLOOR PHY_TO_OFF_PM_RECIEVER(0xbb)
+#define R_VDD1_VROOF PHY_TO_OFF_PM_RECIEVER(0xbc)
+#define R_VDD1_STEP PHY_TO_OFF_PM_RECIEVER(0xbd)
+
+#define R_VDD2_VSEL PHY_TO_OFF_PM_RECIEVER(0xc7)
+#define R_VDD2_VMODE_CFG PHY_TO_OFF_PM_RECIEVER(0xc8)
+#define R_VDD2_VFLOOR PHY_TO_OFF_PM_RECIEVER(0xc9)
+#define R_VDD2_VROOF PHY_TO_OFF_PM_RECIEVER(0xca)
+#define R_VDD2_STEP PHY_TO_OFF_PM_RECIEVER(0xcb)
+
+/* R_DCDC_GLOBAL_CFG register, SMARTREFLEX_ENABLE valuws */
+#define DCDC_GLOBAL_CFG_ENABLE_SRFLX 0x08
+
+/* VDDs*/
+#define PRCM_VDD1 1
+#define PRCM_VDD2 2
+#define PRCM_MAX_SYSC_REGS 30
+
+/* XXX: These should be removed/moved from here once we have a working DVFS
+ implementation in place */
+#define AT_3430 1 /*3430 ES 1.0 */
+#define AT_3430_ES2 2 /*3430 ES 2.0 */
+
+#define ID_OPP 0xE2 /*OPP*/
+
+/* DEVICE ID/DPLL ID/CLOCK ID: bits 28-31 for OMAP type */
+#define OMAP_TYPE_SHIFT 28
+#define OMAP_TYPE_MASK 0xF
+/* OPP ID: bits: 0-4 for OPP number */
+#define OPP_NO_POS 0
+#define OPP_NO_MASK 0x1F
+/* OPP ID: bits: 5-6 for VDD */
+#define VDD_NO_POS 5
+#define VDD_NO_MASK 0x3
+/* Other IDs: bits 20-27 for ID type */
+/* These IDs have bits 25,26,27 as 1 */
+#define OTHER_ID_TYPE_SHIFT 20
+#define OTHER_ID_TYPE_MASK 0xFF
+
+#define OTHER_ID_TYPE(X) ((X & OTHER_ID_TYPE_MASK) << OTHER_ID_TYPE_SHIFT)
+#define ID_OPP_NO(X) ((X & OPP_NO_MASK) << OPP_NO_POS)
+#define ID_VDD(X) ((X & VDD_NO_MASK) << VDD_NO_POS)
+#define OMAP(X) ((X >> OMAP_TYPE_SHIFT) & OMAP_TYPE_MASK)
+#define get_opp_no(X) ((X >> OPP_NO_POS) & OPP_NO_MASK)
+#define get_vdd(X) ((X >> VDD_NO_POS) & VDD_NO_MASK)
+
+/* VDD1 OPPs */
+#define PRCM_VDD1_OPP1 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
+ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x1))
+#define PRCM_VDD1_OPP2 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
+ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x2))
+#define PRCM_VDD1_OPP3 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
+ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x3))
+#define PRCM_VDD1_OPP4 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
+ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x4))
+#define PRCM_VDD1_OPP5 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
+ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x5))
+#define PRCM_NO_VDD1_OPPS 5
+
+
+/* VDD2 OPPs */
+#define PRCM_VDD2_OPP1 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
+ ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x1))
+#define PRCM_VDD2_OPP2 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
+ ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x2))
+#define PRCM_VDD2_OPP3 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
+ ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x3))
+#define PRCM_NO_VDD2_OPPS 3
+/* XXX: end remove/move */
+
+
+/* XXX: find more appropriate place for these once DVFS is in place */
extern u32 current_vdd1_opp;
extern u32 current_vdd2_opp;
-extern struct kset power_subsys;

-extern inline int loop_wait(u32 *lcnt, u32 *rcnt, u32 delay);
-extern void omap_udelay(u32 udelay);
+/*
+ * Smartreflex module enable/disable interface.
+ * NOTE: if smartreflex is not enabled from sysfs, these functions will not
+ * do anything.
+ */
+#if defined(CONFIG_ARCH_OMAP34XX) && defined(CONFIG_TWL4030_CORE)
+void enable_smartreflex(int srid);
+void disable_smartreflex(int srid);
+#else
+static inline void enable_smartreflex(int srid) {}
+static inline void disable_smartreflex(int srid) {}
+#endif
+
+
+#endif
+

diff --git a/include/asm-arm/arch-omap/omap34xx.h b/include/asm-arm/arch-omap/omap34xx.h
index 6a0459a..3667fd6 100644
--- a/include/asm-arm/arch-omap/omap34xx.h
+++ b/include/asm-arm/arch-omap/omap34xx.h
@@ -54,6 +54,8 @@
#define OMAP34XX_HSUSB_HOST_BASE (L4_34XX_BASE + 0x64000)
#define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000)
#define IRQ_SIR_IRQ 0x0040
+#define OMAP34XX_SR1_BASE 0x480C9000
+#define OMAP34XX_SR2_BASE 0x480CB000


#if defined(CONFIG_ARCH_OMAP3430)
--
1.5.4.3

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Kalle Jokiniemi
2008-06-02 11:30:14 UTC
Permalink
- Changed register accesses to use prm_{read,write}_mod_reg and
prm_{set,clear,rmw}_mod_reg_bits() functions instread of
"REG_X = REG_Y" type accesses.

- Changed direct register clock enables/disables to clockframework calls.

- replaced cpu-related #ifdefs with if (cpu_is_xxxx()) calls.

- removed EFUSE related ifdefs

- added smartreflex_disable/enable calls to pm34xx.c suspend function.

- Added "SmartReflex support" entry into Kconfig under "System type->TI OMAP
Implementations". It depends on ARCH_OMAP34XX and TWL4030_CORE.

Signed-off-by: Kalle Jokiniemi <ext-***@nokia.com>
---
arch/arm/mach-omap2/Makefile | 3 +
arch/arm/mach-omap2/pm34xx.c | 9 +
arch/arm/mach-omap2/smartreflex.c | 457 ++++++++++++++++++++++---------------
arch/arm/mach-omap2/smartreflex.h | 2 +-
arch/arm/plat-omap/Kconfig | 17 ++
5 files changed, 302 insertions(+), 186 deletions(-)

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 50c6657..f645b6e 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -25,6 +25,9 @@ obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
obj-$(CONFIG_PM_DEBUG) += pm-debug.o
endif

+# SmartReflex driver
+obj-$(CONFIG_OMAP_SMARTREFLEX) += smartreflex.o
+
# Clock framework
obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o
obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 7e775cc..3da4f47 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -36,6 +36,7 @@

#include "prm.h"
#include "pm.h"
+#include "smartreflex.h"

struct power_state {
struct powerdomain *pwrdm;
@@ -256,6 +257,10 @@ static int omap3_pm_suspend(void)
struct power_state *pwrst;
int state, ret = 0;

+ /* XXX Disable smartreflex before entering suspend */
+ disable_smartreflex(SR1);
+ disable_smartreflex(SR2);
+
/* Read current next_pwrsts */
list_for_each_entry(pwrst, &pwrst_list, node)
pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
@@ -287,6 +292,10 @@ restore:
printk(KERN_INFO "Successfully put all powerdomains "
"to target state\n");

+ /* XXX Enable smartreflex after suspend */
+ enable_smartreflex(SR1);
+ enable_smartreflex(SR2);
+
return ret;
}

diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index dae7460..253369b 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -3,6 +3,9 @@
*
* OMAP34XX SmartReflex Voltage Control
*
+ * Copyright (C) 2008 Nokia Corporation
+ * Kalle Jokiniemi
+ *
* Copyright (C) 2007 Texas Instruments, Inc.
* Lesly A M <***@ti.com>
*
@@ -20,13 +23,15 @@
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/sysfs.h>
-
-#include <asm/arch/prcm.h>
-#include <asm/arch/power_companion.h>
+#include <linux/kobject.h>
+#include <linux/i2c/twl4030.h>
#include <linux/io.h>

-#include "prcm-regs.h"
+#include <asm/arch/omap34xx.h>
+
+#include "prm.h"
#include "smartreflex.h"
+#include "prm-regbits-34xx.h"


/* #define DEBUG_SR 1 */
@@ -37,11 +42,16 @@
# define DPRINTK(fmt, args...)
#endif

+/* XXX: These should be relocated where-ever the OPP implementation will be */
+u32 current_vdd1_opp;
+u32 current_vdd2_opp;
+
struct omap_sr{
int srid;
int is_sr_reset;
int is_autocomp_active;
struct clk *fck;
+ u32 clk_length;
u32 req_opp_no;
u32 opp1_nvalue, opp2_nvalue, opp3_nvalue, opp4_nvalue, opp5_nvalue;
u32 senp_mod, senn_mod;
@@ -53,6 +63,7 @@ static struct omap_sr sr1 = {
.srid = SR1,
.is_sr_reset = 1,
.is_autocomp_active = 0,
+ .clk_length = 0,
.srbase_addr = OMAP34XX_SR1_BASE,
};

@@ -60,6 +71,7 @@ static struct omap_sr sr2 = {
.srid = SR2,
.is_sr_reset = 1,
.is_autocomp_active = 0,
+ .clk_length = 0,
.srbase_addr = OMAP34XX_SR2_BASE,
};

@@ -85,8 +97,6 @@ static inline u32 sr_read_reg(struct omap_sr *sr, int offset)
return omap_readl(sr->srbase_addr + offset);
}

-
-#ifndef USE_EFUSE_VALUES
static void cal_reciprocal(u32 sensor, u32 *sengain, u32 *rnsen)
{
u32 gn, rn, mul;
@@ -100,7 +110,21 @@ static void cal_reciprocal(u32 sensor, u32 *sengain, u32 *rnsen)
}
}
}
-#endif
+
+static void sr_clk_get(struct omap_sr *sr)
+{
+ if (sr->srid == SR1) {
+ sr->fck = clk_get(NULL, "sr1_fck");
+ if (IS_ERR(sr->fck))
+ printk(KERN_ERR "Could not get sr1_fck\n");
+
+ } else if (sr->srid == SR2) {
+ sr->fck = clk_get(NULL, "sr2_fck");
+ if (IS_ERR(sr->fck))
+ printk(KERN_ERR "Could not get sr2_fck\n");
+
+ }
+}

static int sr_clk_enable(struct omap_sr *sr)
{
@@ -131,20 +155,48 @@ static int sr_clk_disable(struct omap_sr *sr)
return 0;
}

+static void sr_set_clk_length(struct omap_sr *sr)
+{
+ struct clk *osc_sys_ck;
+ u32 sys_clk = 0;
+
+ osc_sys_ck = clk_get(NULL, "osc_sys_ck");
+ sys_clk = clk_get_rate(osc_sys_ck);
+ clk_put(osc_sys_ck);
+
+ switch (sys_clk) {
+ case 12000000:
+ sr->clk_length = SRCLKLENGTH_12MHZ_SYSCLK;
+ break;
+ case 13000000:
+ sr->clk_length = SRCLKLENGTH_13MHZ_SYSCLK;
+ break;
+ case 19200000:
+ sr->clk_length = SRCLKLENGTH_19MHZ_SYSCLK;
+ break;
+ case 26000000:
+ sr->clk_length = SRCLKLENGTH_26MHZ_SYSCLK;
+ break;
+ case 38400000:
+ sr->clk_length = SRCLKLENGTH_38MHZ_SYSCLK;
+ break;
+ default :
+ printk(KERN_ERR "Invalid sysclk value: %d\n", sys_clk);
+ break;
+ }
+}
+
+/*
+ * TODO: once EFUSE is available, it should be used instead of these
+ * pre-calculated values.
+ */
static void sr_set_nvalues(struct omap_sr *sr)
{
-#ifdef USE_EFUSE_VALUES
- u32 n1, n2;
-#else
u32 senpval, sennval;
u32 senpgain, senngain;
u32 rnsenp, rnsenn;
-#endif

if (sr->srid == SR1) {
-#ifdef USE_EFUSE_VALUES
- /* Read values for VDD1 from EFUSE */
-#else
/* since E-Fuse Values are not available, calculating the
* reciprocal of the SenN and SenP values for SR1
*/
@@ -216,15 +268,16 @@ static void sr_set_nvalues(struct omap_sr *sr)
(rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
(rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));

+ /* XXX The clocks are enabled in the startup and NVALUE is
+ * set also there. Disabling this for now, but this could
+ * be related to dynamic sleep during boot */
+#if 0
sr_clk_enable(sr);
sr_write_reg(sr, NVALUERECIPROCAL, sr->opp3_nvalue);
sr_clk_disable(sr);
-
#endif
+
} else if (sr->srid == SR2) {
-#ifdef USE_EFUSE_VALUES
- /* Read values for VDD2 from EFUSE */
-#else
/* since E-Fuse Values are not available, calculating the
* reciprocal of the SenN and SenP values for SR2
*/
@@ -269,8 +322,6 @@ static void sr_set_nvalues(struct omap_sr *sr)
(senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
(rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
(rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
-
-#endif
}

}
@@ -281,122 +332,145 @@ static void sr_configure_vp(int srid)

if (srid == SR1) {
vpconfig = PRM_VP1_CONFIG_ERROROFFSET | PRM_VP1_CONFIG_ERRORGAIN
- | PRM_VP1_CONFIG_INITVOLTAGE | PRM_VP1_CONFIG_TIMEOUTEN;
-
- PRM_VP1_CONFIG = vpconfig;
- PRM_VP1_VSTEPMIN = PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN |
- PRM_VP1_VSTEPMIN_VSTEPMIN;
-
- PRM_VP1_VSTEPMAX = PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX |
- PRM_VP1_VSTEPMAX_VSTEPMAX;
-
- PRM_VP1_VLIMITTO = PRM_VP1_VLIMITTO_VDDMAX |
- PRM_VP1_VLIMITTO_VDDMIN | PRM_VP1_VLIMITTO_TIMEOUT;
-
- PRM_VP1_CONFIG |= PRM_VP1_CONFIG_INITVDD;
- PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_INITVDD;
+ | PRM_VP1_CONFIG_INITVOLTAGE
+ | PRM_VP1_CONFIG_TIMEOUTEN;
+
+ prm_write_mod_reg(vpconfig, OMAP3430_GR_MOD,
+ OMAP3_PRM_VP1_CONFIG_OFFSET);
+ prm_write_mod_reg(PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN |
+ PRM_VP1_VSTEPMIN_VSTEPMIN,
+ OMAP3430_GR_MOD,
+ OMAP3_PRM_VP1_VSTEPMIN_OFFSET);
+
+ prm_write_mod_reg(PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX |
+ PRM_VP1_VSTEPMAX_VSTEPMAX,
+ OMAP3430_GR_MOD,
+ OMAP3_PRM_VP1_VSTEPMAX_OFFSET);
+
+ prm_write_mod_reg(PRM_VP1_VLIMITTO_VDDMAX |
+ PRM_VP1_VLIMITTO_VDDMIN |
+ PRM_VP1_VLIMITTO_TIMEOUT,
+ OMAP3430_GR_MOD,
+ OMAP3_PRM_VP1_VLIMITTO_OFFSET);
+
+ /* Trigger initVDD value copy to voltage processor */
+ prm_set_mod_reg_bits(PRM_VP1_CONFIG_INITVDD, OMAP3430_GR_MOD,
+ OMAP3_PRM_VP1_CONFIG_OFFSET);
+ /* Clear initVDD copy trigger bit */
+ prm_clear_mod_reg_bits(PRM_VP1_CONFIG_INITVDD, OMAP3430_GR_MOD,
+ OMAP3_PRM_VP1_CONFIG_OFFSET);

} else if (srid == SR2) {
vpconfig = PRM_VP2_CONFIG_ERROROFFSET | PRM_VP2_CONFIG_ERRORGAIN
- | PRM_VP2_CONFIG_INITVOLTAGE | PRM_VP2_CONFIG_TIMEOUTEN;
-
- PRM_VP2_CONFIG = vpconfig;
- PRM_VP2_VSTEPMIN = PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN |
- PRM_VP2_VSTEPMIN_VSTEPMIN;
-
- PRM_VP2_VSTEPMAX = PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX |
- PRM_VP2_VSTEPMAX_VSTEPMAX;
-
- PRM_VP2_VLIMITTO = PRM_VP2_VLIMITTO_VDDMAX |
- PRM_VP2_VLIMITTO_VDDMIN | PRM_VP2_VLIMITTO_TIMEOUT;
-
- PRM_VP2_CONFIG |= PRM_VP2_CONFIG_INITVDD;
- PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_INITVDD;
+ | PRM_VP2_CONFIG_INITVOLTAGE
+ | PRM_VP2_CONFIG_TIMEOUTEN;
+
+ prm_write_mod_reg(vpconfig, OMAP3430_GR_MOD,
+ OMAP3_PRM_VP2_CONFIG_OFFSET);
+ prm_write_mod_reg(PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN |
+ PRM_VP2_VSTEPMIN_VSTEPMIN,
+ OMAP3430_GR_MOD,
+ OMAP3_PRM_VP2_VSTEPMIN_OFFSET);
+
+ prm_write_mod_reg(PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX |
+ PRM_VP2_VSTEPMAX_VSTEPMAX,
+ OMAP3430_GR_MOD,
+ OMAP3_PRM_VP2_VSTEPMAX_OFFSET);
+
+ prm_write_mod_reg(PRM_VP2_VLIMITTO_VDDMAX |
+ PRM_VP2_VLIMITTO_VDDMIN |
+ PRM_VP2_VLIMITTO_TIMEOUT,
+ OMAP3430_GR_MOD,
+ OMAP3_PRM_VP2_VLIMITTO_OFFSET);
+
+ /* Trigger initVDD value copy to voltage processor */
+ prm_set_mod_reg_bits(PRM_VP2_CONFIG_INITVDD, OMAP3430_GR_MOD,
+ OMAP3_PRM_VP2_CONFIG_OFFSET);
+ /* Reset initVDD copy trigger bit */
+ prm_clear_mod_reg_bits(PRM_VP2_CONFIG_INITVDD, OMAP3430_GR_MOD,
+ OMAP3_PRM_VP2_CONFIG_OFFSET);

}
}

static void sr_configure_vc(void)
{
- PRM_VC_SMPS_SA =
- (R_SRI2C_SLAVE_ADDR << PRM_VC_SMPS_SA1_SHIFT) |
- (R_SRI2C_SLAVE_ADDR << PRM_VC_SMPS_SA0_SHIFT);
-
- PRM_VC_SMPS_VOL_RA = (R_VDD2_SR_CONTROL << PRM_VC_SMPS_VOLRA1_SHIFT) |
- (R_VDD1_SR_CONTROL << PRM_VC_SMPS_VOLRA0_SHIFT);
-
- PRM_VC_CMD_VAL_0 = (PRM_VC_CMD_VAL0_ON << PRM_VC_CMD_ON_SHIFT) |
- (PRM_VC_CMD_VAL0_ONLP << PRM_VC_CMD_ONLP_SHIFT) |
- (PRM_VC_CMD_VAL0_RET << PRM_VC_CMD_RET_SHIFT) |
- (PRM_VC_CMD_VAL0_OFF << PRM_VC_CMD_OFF_SHIFT);
-
- PRM_VC_CMD_VAL_1 = (PRM_VC_CMD_VAL1_ON << PRM_VC_CMD_ON_SHIFT) |
- (PRM_VC_CMD_VAL1_ONLP << PRM_VC_CMD_ONLP_SHIFT) |
- (PRM_VC_CMD_VAL1_RET << PRM_VC_CMD_RET_SHIFT) |
- (PRM_VC_CMD_VAL1_OFF << PRM_VC_CMD_OFF_SHIFT);
-
- PRM_VC_CH_CONF = PRM_VC_CH_CONF_CMD1 | PRM_VC_CH_CONF_RAV1;
-
- PRM_VC_I2C_CFG = PRM_VC_I2C_CFG_MCODE | PRM_VC_I2C_CFG_HSEN
- | PRM_VC_I2C_CFG_SREN;
+ prm_write_mod_reg((R_SRI2C_SLAVE_ADDR << OMAP3430_SMPS_SA1_SHIFT) |
+ (R_SRI2C_SLAVE_ADDR << OMAP3430_SMPS_SA0_SHIFT),
+ OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_SA_OFFSET);
+
+ prm_write_mod_reg((R_VDD2_SR_CONTROL << OMAP3430_VOLRA1_SHIFT) |
+ (R_VDD1_SR_CONTROL << OMAP3430_VOLRA0_SHIFT),
+ OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET);
+
+ prm_write_mod_reg((OMAP3430_VC_CMD_VAL0_ON <<
+ OMAP3430_VC_CMD_ON_SHIFT) |
+ (OMAP3430_VC_CMD_VAL0_ONLP << OMAP3430_VC_CMD_ONLP_SHIFT) |
+ (OMAP3430_VC_CMD_VAL0_RET << OMAP3430_VC_CMD_RET_SHIFT) |
+ (OMAP3430_VC_CMD_VAL0_OFF << OMAP3430_VC_CMD_OFF_SHIFT),
+ OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_0_OFFSET);
+
+ prm_write_mod_reg((OMAP3430_VC_CMD_VAL1_ON <<
+ OMAP3430_VC_CMD_ON_SHIFT) |
+ (OMAP3430_VC_CMD_VAL1_ONLP << OMAP3430_VC_CMD_ONLP_SHIFT) |
+ (OMAP3430_VC_CMD_VAL1_RET << OMAP3430_VC_CMD_RET_SHIFT) |
+ (OMAP3430_VC_CMD_VAL1_OFF << OMAP3430_VC_CMD_OFF_SHIFT),
+ OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_1_OFFSET);
+
+ prm_write_mod_reg(OMAP3430_CMD1 | OMAP3430_RAV1,
+ OMAP3430_GR_MOD,
+ OMAP3_PRM_VC_CH_CONF_OFFSET);
+
+ prm_write_mod_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN | OMAP3430_SREN,
+ OMAP3430_GR_MOD,
+ OMAP3_PRM_VC_I2C_CFG_OFFSET);

/* Setup voltctrl and other setup times */
+ /* XXX CONFIG_SYSOFFMODE has not been implemented yet */
#ifdef CONFIG_SYSOFFMODE
- PRM_VOLTCTRL = PRM_VOLTCTRL_AUTO_OFF | PRM_VOLTCTRL_AUTO_RET;
- PRM_CLKSETUP = PRM_CLKSETUP_DURATION;
- PRM_VOLTSETUP1 = (PRM_VOLTSETUP_TIME2 << PRM_VOLTSETUP_TIME2_OFFSET) |
- (PRM_VOLTSETUP_TIME1 << PRM_VOLTSETUP_TIME1_OFFSET);
- PRM_VOLTOFFSET = PRM_VOLTOFFSET_DURATION;
- PRM_VOLTSETUP2 = PRM_VOLTSETUP2_DURATION;
+ prm_write_mod_reg(OMAP3430_AUTO_OFF | OMAP3430_AUTO_RET,
+ OMAP3430_GR_MOD,
+ OMAP3_PRM_VOLTCTRL_OFFSET);
+
+ prm_write_mod_reg(OMAP3430_CLKSETUP_DURATION, OMAP3430_GR_MOD,
+ OMAP3_PRM_CLKSETUP_OFFSET);
+ prm_write_mod_reg((OMAP3430_VOLTSETUP_TIME2 <<
+ OMAP3430_VOLTSETUP_TIME2_OFFSET) |
+ (OMAP3430_VOLTSETUP_TIME1 <<
+ OMAP3430_VOLTSETUP_TIME1_OFFSET),
+ OMAP3430_GR_MOD, OMAP3_PRM_VOLTSETUP1_OFFSET);
+
+ prm_write_mod_reg(OMAP3430_VOLTOFFSET_DURATION, OMAP3430_GR_MOD,
+ OMAP3_PRM_VOLTOFFSET_OFFSET);
+ prm_write_mod_reg(OMAP3430_VOLTSETUP2_DURATION, OMAP3430_GR_MOD,
+ OMAP3_PRM_VOLTSETUP2_OFFSET);
#else
- PRM_VOLTCTRL |= PRM_VOLTCTRL_AUTO_RET;
+ prm_set_mod_reg_bits(OMAP3430_AUTO_RET, OMAP3430_GR_MOD,
+ OMAP3_PRM_VOLTCTRL_OFFSET);
#endif

}

-
static void sr_configure(struct omap_sr *sr)
{
- u32 sys_clk, sr_clk_length = 0;
u32 sr_config;
u32 senp_en , senn_en;

+ if (sr->clk_length == 0)
+ sr_set_clk_length(sr);
+
senp_en = sr->senp_mod;
senn_en = sr->senn_mod;
-
- sys_clk = prcm_get_system_clock_speed();
-
- switch (sys_clk) {
- case 12000:
- sr_clk_length = SRCLKLENGTH_12MHZ_SYSCLK;
- break;
- case 13000:
- sr_clk_length = SRCLKLENGTH_13MHZ_SYSCLK;
- break;
- case 19200:
- sr_clk_length = SRCLKLENGTH_19MHZ_SYSCLK;
- break;
- case 26000:
- sr_clk_length = SRCLKLENGTH_26MHZ_SYSCLK;
- break;
- case 38400:
- sr_clk_length = SRCLKLENGTH_38MHZ_SYSCLK;
- break;
- default :
- printk(KERN_ERR "Invalid sysclk value\n");
- break;
- }
-
- DPRINTK(KERN_DEBUG "SR : sys clk %lu\n", sys_clk);
if (sr->srid == SR1) {
sr_config = SR1_SRCONFIG_ACCUMDATA |
- (sr_clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
+ (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN |
SRCONFIG_MINMAXAVG_EN |
(senn_en << SRCONFIG_SENNENABLE_SHIFT) |
(senp_en << SRCONFIG_SENPENABLE_SHIFT) |
SRCONFIG_DELAYCTRL;
-
+ DPRINTK(KERN_DEBUG "setting SRCONFIG1 to 0x%08lx\n",
+ (unsigned long int) sr_config);
sr_write_reg(sr, SRCONFIG, sr_config);

sr_write_reg(sr, AVGWEIGHT, SR1_AVGWEIGHT_SENPAVGWEIGHT |
@@ -408,18 +482,18 @@ static void sr_configure(struct omap_sr *sr)

} else if (sr->srid == SR2) {
sr_config = SR2_SRCONFIG_ACCUMDATA |
- (sr_clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
+ (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN |
SRCONFIG_MINMAXAVG_EN |
(senn_en << SRCONFIG_SENNENABLE_SHIFT) |
(senp_en << SRCONFIG_SENPENABLE_SHIFT) |
SRCONFIG_DELAYCTRL;

+ DPRINTK(KERN_DEBUG "setting SRCONFIG2 to 0x%08lx\n",
+ (unsigned long int) sr_config);
sr_write_reg(sr, SRCONFIG, sr_config);
-
sr_write_reg(sr, AVGWEIGHT, SR2_AVGWEIGHT_SENPAVGWEIGHT |
SR2_AVGWEIGHT_SENNAVGWEIGHT);
-
sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK |
SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
(SR2_ERRWEIGHT | SR2_ERRMAXLIMIT | SR2_ERRMINLIMIT));
@@ -476,7 +550,6 @@ static void sr_enable(struct omap_sr *sr, u32 target_opp_no)

if (current_nvalue == nvalue_reciprocal) {
DPRINTK("System is already at the desired voltage level\n");
- return;
}

sr_write_reg(sr, NVALUERECIPROCAL, nvalue_reciprocal);
@@ -485,18 +558,18 @@ static void sr_enable(struct omap_sr *sr, u32 target_opp_no)
sr_modify_reg(sr, ERRCONFIG,
(ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST),
(ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST));
-
if (sr->srid == SR1) {
/* Enable VP1 */
- PRM_VP1_CONFIG |= PRM_VP1_CONFIG_VPENABLE;
+ prm_set_mod_reg_bits(PRM_VP1_CONFIG_VPENABLE, OMAP3430_GR_MOD,
+ OMAP3_PRM_VP1_CONFIG_OFFSET);
} else if (sr->srid == SR2) {
/* Enable VP2 */
- PRM_VP2_CONFIG |= PRM_VP2_CONFIG_VPENABLE;
+ prm_set_mod_reg_bits(PRM_VP2_CONFIG_VPENABLE, OMAP3430_GR_MOD,
+ OMAP3_PRM_VP2_CONFIG_OFFSET);
}

/* SRCONFIG - enable SR */
sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE);
-
}

static void sr_disable(struct omap_sr *sr)
@@ -507,11 +580,13 @@ static void sr_disable(struct omap_sr *sr)
sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, ~SRCONFIG_SRENABLE);

if (sr->srid == SR1) {
- /* Enable VP1 */
- PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_VPENABLE;
+ /* Disable VP1 */
+ prm_clear_mod_reg_bits(PRM_VP1_CONFIG_VPENABLE, OMAP3430_GR_MOD,
+ OMAP3_PRM_VP1_CONFIG_OFFSET);
} else if (sr->srid == SR2) {
- /* Enable VP2 */
- PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_VPENABLE;
+ /* Disable VP2 */
+ prm_clear_mod_reg_bits(PRM_VP2_CONFIG_VPENABLE, OMAP3430_GR_MOD,
+ OMAP3_PRM_VP2_CONFIG_OFFSET);
}
}

@@ -574,16 +649,13 @@ void enable_smartreflex(int srid)

if (sr->is_autocomp_active == 1) {
if (sr->is_sr_reset == 1) {
- if (srid == SR1) {
- /* Enable SR clks */
- CM_FCLKEN_WKUP |= SR1_CLK_ENABLE;
- target_opp_no = get_opp_no(current_vdd1_opp);
+ /* Enable SR clks */
+ sr_clk_enable(sr);

- } else if (srid == SR2) {
- /* Enable SR clks */
- CM_FCLKEN_WKUP |= SR2_CLK_ENABLE;
+ if (srid == SR1)
+ target_opp_no = get_opp_no(current_vdd1_opp);
+ else if (srid == SR2)
target_opp_no = get_opp_no(current_vdd2_opp);
- }

sr_configure(sr);

@@ -602,15 +674,6 @@ void disable_smartreflex(int srid)
sr = &sr2;

if (sr->is_autocomp_active == 1) {
- if (srid == SR1) {
- /* Enable SR clk */
- CM_FCLKEN_WKUP |= SR1_CLK_ENABLE;
-
- } else if (srid == SR2) {
- /* Enable SR clk */
- CM_FCLKEN_WKUP |= SR2_CLK_ENABLE;
- }
-
if (sr->is_sr_reset == 0) {

sr->is_sr_reset = 1;
@@ -618,17 +681,18 @@ void disable_smartreflex(int srid)
sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE,
~SRCONFIG_SRENABLE);

+ /* Disable SR clk */
+ sr_clk_disable(sr);
if (sr->srid == SR1) {
- /* Disable SR clk */
- CM_FCLKEN_WKUP &= ~SR1_CLK_ENABLE;
- /* Enable VP1 */
- PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_VPENABLE;
-
+ /* Disable VP1 */
+ prm_clear_mod_reg_bits(PRM_VP1_CONFIG_VPENABLE,
+ OMAP3430_GR_MOD,
+ OMAP3_PRM_VP1_CONFIG_OFFSET);
} else if (sr->srid == SR2) {
- /* Disable SR clk */
- CM_FCLKEN_WKUP &= ~SR2_CLK_ENABLE;
- /* Enable VP2 */
- PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_VPENABLE;
+ /* Disable VP2 */
+ prm_clear_mod_reg_bits(PRM_VP2_CONFIG_VPENABLE,
+ OMAP3430_GR_MOD,
+ OMAP3_PRM_VP2_CONFIG_OFFSET);
}
}
}
@@ -638,7 +702,6 @@ void disable_smartreflex(int srid)
/* Voltage Scaling using SR VCBYPASS */
int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel)
{
- int ret;
int sr_status = 0;
u32 vdd, target_opp_no;
u32 vc_bypass_value;
@@ -651,39 +714,53 @@ int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel)
if (vdd == PRCM_VDD1) {
sr_status = sr_stop_vddautocomap(SR1);

- PRM_VC_CMD_VAL_0 = (PRM_VC_CMD_VAL_0 & ~PRM_VC_CMD_ON_MASK) |
- (vsel << PRM_VC_CMD_ON_SHIFT);
+ prm_rmw_mod_reg_bits(OMAP3430_VC_CMD_ON_MASK,
+ (vsel << OMAP3430_VC_CMD_ON_SHIFT),
+ OMAP3430_GR_MOD,
+ OMAP3_PRM_VC_CMD_VAL_0_OFFSET);
reg_addr = R_VDD1_SR_CONTROL;

} else if (vdd == PRCM_VDD2) {
sr_status = sr_stop_vddautocomap(SR2);

- PRM_VC_CMD_VAL_1 = (PRM_VC_CMD_VAL_1 & ~PRM_VC_CMD_ON_MASK) |
- (vsel << PRM_VC_CMD_ON_SHIFT);
+ prm_rmw_mod_reg_bits(OMAP3430_VC_CMD_ON_MASK,
+ (vsel << OMAP3430_VC_CMD_ON_SHIFT),
+ OMAP3430_GR_MOD,
+ OMAP3_PRM_VC_CMD_VAL_1_OFFSET);
reg_addr = R_VDD2_SR_CONTROL;
}

- vc_bypass_value = (vsel << PRM_VC_BYPASS_DATA_SHIFT) |
- (reg_addr << PRM_VC_BYPASS_REGADDR_SHIFT) |
- (R_SRI2C_SLAVE_ADDR << PRM_VC_BYPASS_SLAVEADDR_SHIFT);
+ vc_bypass_value = (vsel << OMAP3430_DATA_SHIFT) |
+ (reg_addr << OMAP3430_REGADDR_SHIFT) |
+ (R_SRI2C_SLAVE_ADDR << OMAP3430_SLAVEADDR_SHIFT);

- PRM_VC_BYPASS_VAL = vc_bypass_value;
+ prm_write_mod_reg(vc_bypass_value, OMAP3430_GR_MOD,
+ OMAP3_PRM_VC_BYPASS_VAL_OFFSET);

- PRM_VC_BYPASS_VAL |= PRM_VC_BYPASS_VALID;
+ vc_bypass_value = prm_set_mod_reg_bits(OMAP3430_VALID, OMAP3430_GR_MOD,
+ OMAP3_PRM_VC_BYPASS_VAL_OFFSET);

- DPRINTK("%s : PRM_VC_BYPASS_VAL %X\n", __func__, PRM_VC_BYPASS_VAL);
- DPRINTK("PRM_IRQST_MPU %X\n", PRM_IRQSTATUS_MPU);
+ DPRINTK("%s : PRM_VC_BYPASS_VAL %X\n", __func__, vc_bypass_value);
+ DPRINTK("PRM_IRQST_MPU %X\n", prm_read_mod_reg(OCP_MOD,
+ OMAP3_PRM_IRQSTATUS_MPU_OFFSET));

- while ((PRM_VC_BYPASS_VAL & PRM_VC_BYPASS_VALID) != 0x0) {
- ret = loop_wait(&loop_cnt, &retries_cnt, 10);
- if (ret != PRCM_PASS) {
+ while ((vc_bypass_value & OMAP3430_VALID) != 0x0) {
+ loop_cnt++;
+ if (retries_cnt > 10) {
printk(KERN_INFO "Loop count exceeded in check SR I2C"
"write\n");
- return ret;
+ return SR_FAIL;
}
+ if (loop_cnt > 50) {
+ retries_cnt++;
+ loop_cnt = 0;
+ udelay(10);
+ }
+ vc_bypass_value = prm_read_mod_reg(OMAP3430_GR_MOD,
+ OMAP3_PRM_VC_BYPASS_VAL_OFFSET);
}

- omap_udelay(T2_SMPS_UPDATE_DELAY);
+ udelay(T2_SMPS_UPDATE_DELAY);

if (sr_status) {
if (vdd == PRCM_VDD1)
@@ -696,13 +773,15 @@ int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel)
}

/* Sysfs interface to select SR VDD1 auto compensation */
-static ssize_t omap_sr_vdd1_autocomp_show(struct kset *subsys, char *buf)
+static ssize_t omap_sr_vdd1_autocomp_show(struct kobject *kobj,
+ struct kobj_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", sr1.is_autocomp_active);
}

-static ssize_t omap_sr_vdd1_autocomp_store(struct kset *subsys,
- const char *buf, size_t n)
+static ssize_t omap_sr_vdd1_autocomp_store(struct kobject *kobj,
+ struct kobj_attribute *attr,
+ const char *buf, size_t n)
{
u32 current_vdd1opp_no;
unsigned short value;
@@ -722,7 +801,7 @@ static ssize_t omap_sr_vdd1_autocomp_store(struct kset *subsys,
return n;
}

-static struct subsys_attribute sr_vdd1_autocomp = {
+static struct kobj_attribute sr_vdd1_autocomp = {
.attr = {
.name = __stringify(sr_vdd1_autocomp),
.mode = 0644,
@@ -732,13 +811,15 @@ static struct subsys_attribute sr_vdd1_autocomp = {
};

/* Sysfs interface to select SR VDD2 auto compensation */
-static ssize_t omap_sr_vdd2_autocomp_show(struct kset *subsys, char *buf)
+static ssize_t omap_sr_vdd2_autocomp_show(struct kobject *kobj,
+ struct kobj_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", sr2.is_autocomp_active);
}

-static ssize_t omap_sr_vdd2_autocomp_store(struct kset *subsys,
- const char *buf, size_t n)
+static ssize_t omap_sr_vdd2_autocomp_store(struct kobject *kobj,
+ struct kobj_attribute *attr,
+ const char *buf, size_t n)
{
u32 current_vdd2opp_no;
unsigned short value;
@@ -758,7 +839,7 @@ static ssize_t omap_sr_vdd2_autocomp_store(struct kset *subsys,
return n;
}

-static struct subsys_attribute sr_vdd2_autocomp = {
+static struct kobj_attribute sr_vdd2_autocomp = {
.attr = {
.name = __stringify(sr_vdd2_autocomp),
.mode = 0644,
@@ -774,15 +855,19 @@ static int __init omap3_sr_init(void)
int ret = 0;
u8 RdReg;

-#ifdef CONFIG_ARCH_OMAP34XX
- sr1.fck = clk_get(NULL, "sr1_fck");
- if (IS_ERR(sr1.fck))
- printk(KERN_ERR "Could not get sr1_fck\n");
-
- sr2.fck = clk_get(NULL, "sr2_fck");
- if (IS_ERR(sr2.fck))
- printk(KERN_ERR "Could not get sr2_fck\n");
-#endif /* #ifdef CONFIG_ARCH_OMAP34XX */
+ if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+ current_vdd1_opp = PRCM_VDD1_OPP3;
+ current_vdd2_opp = PRCM_VDD2_OPP3;
+ } else {
+ current_vdd1_opp = PRCM_VDD1_OPP1;
+ current_vdd2_opp = PRCM_VDD1_OPP1;
+ }
+ if (cpu_is_omap34xx()) {
+ sr_clk_get(&sr1);
+ sr_clk_get(&sr2);
+ }
+ sr_set_clk_length(&sr1);
+ sr_set_clk_length(&sr2);

/* Call the VPConfig, VCConfig, set N Values. */
sr_set_nvalues(&sr1);
@@ -794,22 +879,24 @@ static int __init omap3_sr_init(void)
sr_configure_vc();

/* Enable SR on T2 */
- ret = t2_in(PM_RECEIVER, &RdReg, R_DCDC_GLOBAL_CFG);
- RdReg |= DCDC_GLOBAL_CFG_ENABLE_SRFLX;
- ret |= t2_out(PM_RECEIVER, RdReg, R_DCDC_GLOBAL_CFG);
+ ret = twl4030_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &RdReg,
+ R_DCDC_GLOBAL_CFG);

+ RdReg |= DCDC_GLOBAL_CFG_ENABLE_SRFLX;
+ ret |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, RdReg,
+ R_DCDC_GLOBAL_CFG);

printk(KERN_INFO "SmartReflex driver initialized\n");

- ret = subsys_create_file(&power_subsys, &sr_vdd1_autocomp);
+ ret = sysfs_create_file(power_kobj, &sr_vdd1_autocomp.attr);
if (ret)
- printk(KERN_ERR "subsys_create_file failed: %d\n", ret);
+ printk(KERN_ERR "sysfs_create_file failed: %d\n", ret);

- ret = subsys_create_file(&power_subsys, &sr_vdd2_autocomp);
+ ret = sysfs_create_file(power_kobj, &sr_vdd2_autocomp.attr);
if (ret)
- printk(KERN_ERR "subsys_create_file failed: %d\n", ret);
+ printk(KERN_ERR "sysfs_create_file failed: %d\n", ret);

return 0;
}

-arch_initcall(omap3_sr_init);
+late_initcall(omap3_sr_init);
diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
index 2091a15..d7ccd46 100644
--- a/arch/arm/mach-omap2/smartreflex.h
+++ b/arch/arm/mach-omap2/smartreflex.h
@@ -238,7 +238,7 @@ extern u32 current_vdd2_opp;
* NOTE: if smartreflex is not enabled from sysfs, these functions will not
* do anything.
*/
-#if defined(CONFIG_ARCH_OMAP34XX) && defined(CONFIG_TWL4030_CORE)
+#ifdef CONFIG_OMAP_SMARTREFLEX
void enable_smartreflex(int srid);
void disable_smartreflex(int srid);
#else
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index b085b07..53745ce 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -56,6 +56,23 @@ config OMAP_DEBUG_CLOCKDOMAIN
for every clockdomain register write. However, the
extra detail costs some memory.

+config OMAP_SMARTREFLEX
+ bool "SmartReflex support"
+ depends on ARCH_OMAP34XX && TWL4030_CORE
+ help
+ Say Y if you want to enable SmartReflex.
+
+ SmartReflex can perform continuous dynamic voltage
+ scaling around the nominal operating point voltage
+ according to silicon characteristics and operating
+ conditions. Enabling SmartReflex reduces power
+ consumption.
+
+ Please note, that by default SmartReflex is only
+ initialized. To enable the automatic voltage
+ compensation for VDD1 and VDD2, user must write 1 to
+ /sys/power/sr_vddX_autocomp, where X is 1 or 2.
+
config OMAP_RESET_CLOCKS
bool "Reset unused clocks during boot"
depends on ARCH_OMAP
--
1.5.4.3

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Kalle Jokiniemi
2008-06-02 11:30:13 UTC
Permalink
Added new register and bit definitions to enable Smartreflex driver integration.
Also PRM_VC_SMPS_SA bit definitions' naming was changed to match the naming of
other similar bit definitions.

Signed-off-by: Kalle Jokiniemi <ext-***@nokia.com>
---
arch/arm/mach-omap2/prm-regbits-34xx.h | 27 ++++++--
arch/arm/mach-omap2/smartreflex.h | 124 ++++++++++++++++++++++++++++++-
include/asm-arm/arch-omap/omap34xx.h | 2 +
3 files changed, 144 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index c6a7940..f82b5a7 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -435,10 +435,10 @@
/* PM_PWSTST_EMU specific bits */

/* PRM_VC_SMPS_SA */
-#define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT 16
-#define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16)
-#define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT 0
-#define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0)
+#define OMAP3430_SMPS_SA1_SHIFT 16
+#define OMAP3430_SMPS_SA1_MASK (0x7f << 16)
+#define OMAP3430_SMPS_SA0_SHIFT 0
+#define OMAP3430_SMPS_SA0_MASK (0x7f << 0)

/* PRM_VC_SMPS_VOL_RA */
#define OMAP3430_VOLRA1_SHIFT 16
@@ -452,7 +452,7 @@
#define OMAP3430_CMDRA0_SHIFT 0
#define OMAP3430_CMDRA0_MASK (0xff << 0)

-/* PRM_VC_CMD_VAL_0 specific bits */
+/* PRM_VC_CMD_VAL */
#define OMAP3430_VC_CMD_ON_SHIFT 24
#define OMAP3430_VC_CMD_ON_MASK (0xFF << 24)
#define OMAP3430_VC_CMD_ONLP_SHIFT 16
@@ -462,7 +462,17 @@
#define OMAP3430_VC_CMD_OFF_SHIFT 0
#define OMAP3430_VC_CMD_OFF_MASK (0xFF << 0)

+/* PRM_VC_CMD_VAL_0 specific bits */
+#define OMAP3430_VC_CMD_VAL0_ON (0x3 << 4)
+#define OMAP3430_VC_CMD_VAL0_ONLP (0x3 << 3)
+#define OMAP3430_VC_CMD_VAL0_RET (0x3 << 3)
+#define OMAP3430_VC_CMD_VAL0_OFF (0x3 << 3)
+
/* PRM_VC_CMD_VAL_1 specific bits */
+#define OMAP3430_VC_CMD_VAL1_ON (0xB << 2)
+#define OMAP3430_VC_CMD_VAL1_ONLP (0x3 << 3)
+#define OMAP3430_VC_CMD_VAL1_RET (0x3 << 3)
+#define OMAP3430_VC_CMD_VAL1_OFF (0x3 << 3)

/* PRM_VC_CH_CONF */
#define OMAP3430_CMD1 (1 << 20)
@@ -521,6 +531,13 @@
#define OMAP3430_AUTO_RET (1 << 1)
#define OMAP3430_AUTO_SLEEP (1 << 0)

+/* Constants to define setup durations */
+#define OMAP3430_CLKSETUP_DURATION 0xff
+#define OMAP3430_VOLTSETUP_TIME2 0xfff
+#define OMAP3430_VOLTSETUP_TIME1 0xfff
+#define OMAP3430_VOLTOFFSET_DURATION 0xff
+#define OMAP3430_VOLTSETUP2_DURATION 0xff
+
/* PRM_SRAM_PCHARGE */
#define OMAP3430_PCHARGE_TIME_SHIFT 0
#define OMAP3430_PCHARGE_TIME_MASK (0xff << 0)
diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
index 62907ef..2091a15 100644
--- a/arch/arm/mach-omap2/smartreflex.h
+++ b/arch/arm/mach-omap2/smartreflex.h
@@ -1,5 +1,10 @@
+#ifndef __ARCH_ARM_MACH_OMAP3_SMARTREFLEX_H
+#define __ARCH_ARM_MACH_OMAP3_SMARTREFLEX_H
/*
- * linux/arch/arm/mach-omap3/smartreflex.h
+ * linux/arch/arm/mach-omap2/smartreflex.h
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Kalle Jokiniemi
*
* Copyright (C) 2007 Texas Instruments, Inc.
* Lesly A M <***@ti.com>
@@ -9,6 +14,21 @@
* published by the Free Software Foundation.
*/

+#define PHY_TO_OFF_PM_MASTER(p) (p - 0x36)
+#define PHY_TO_OFF_PM_RECIEVER(p) (p - 0x5b)
+#define PHY_TO_OFF_PM_INT(p) (p - 0x2e)
+
+/* SMART REFLEX REG ADDRESS OFFSET */
+#define SRCONFIG 0x00
+#define SRSTATUS 0x04
+#define SENVAL 0x08
+#define SENMIN 0x0C
+#define SENMAX 0x10
+#define SENAVG 0x14
+#define AVGWEIGHT 0x18
+#define NVALUERECIPROCAL 0x1C
+#define SENERROR 0x20
+#define ERRCONFIG 0x24

/* SR Modules */
#define SR1 1
@@ -127,10 +147,106 @@
#define SR2_ERRMAXLIMIT (0x02 << 8)
#define SR2_ERRMINLIMIT (0xF9 << 0)

+/* T2 SMART REFLEX */
+#define R_SRI2C_SLAVE_ADDR 0x12
+#define R_VDD1_SR_CONTROL 0x00
+#define R_VDD2_SR_CONTROL 0x01
+#define T2_SMPS_UPDATE_DELAY 360 /* In uSec */
+
+/* Vmode control */
+#define R_DCDC_GLOBAL_CFG PHY_TO_OFF_PM_RECIEVER(0x61)
+
+#define R_VDD1_VSEL PHY_TO_OFF_PM_RECIEVER(0xb9)
+#define R_VDD1_VMODE_CFG PHY_TO_OFF_PM_RECIEVER(0xba)
+#define R_VDD1_VFLOOR PHY_TO_OFF_PM_RECIEVER(0xbb)
+#define R_VDD1_VROOF PHY_TO_OFF_PM_RECIEVER(0xbc)
+#define R_VDD1_STEP PHY_TO_OFF_PM_RECIEVER(0xbd)
+
+#define R_VDD2_VSEL PHY_TO_OFF_PM_RECIEVER(0xc7)
+#define R_VDD2_VMODE_CFG PHY_TO_OFF_PM_RECIEVER(0xc8)
+#define R_VDD2_VFLOOR PHY_TO_OFF_PM_RECIEVER(0xc9)
+#define R_VDD2_VROOF PHY_TO_OFF_PM_RECIEVER(0xca)
+#define R_VDD2_STEP PHY_TO_OFF_PM_RECIEVER(0xcb)
+
+/* R_DCDC_GLOBAL_CFG register, SMARTREFLEX_ENABLE valuws */
+#define DCDC_GLOBAL_CFG_ENABLE_SRFLX 0x08
+
+/* VDDs*/
+#define PRCM_VDD1 1
+#define PRCM_VDD2 2
+#define PRCM_MAX_SYSC_REGS 30
+
+/* XXX: These should be removed/moved from here once we have a working DVFS
+ implementation in place */
+#define AT_3430 1 /*3430 ES 1.0 */
+#define AT_3430_ES2 2 /*3430 ES 2.0 */
+
+#define ID_OPP 0xE2 /*OPP*/
+
+/* DEVICE ID/DPLL ID/CLOCK ID: bits 28-31 for OMAP type */
+#define OMAP_TYPE_SHIFT 28
+#define OMAP_TYPE_MASK 0xF
+/* OPP ID: bits: 0-4 for OPP number */
+#define OPP_NO_POS 0
+#define OPP_NO_MASK 0x1F
+/* OPP ID: bits: 5-6 for VDD */
+#define VDD_NO_POS 5
+#define VDD_NO_MASK 0x3
+/* Other IDs: bits 20-27 for ID type */
+/* These IDs have bits 25,26,27 as 1 */
+#define OTHER_ID_TYPE_SHIFT 20
+#define OTHER_ID_TYPE_MASK 0xFF
+
+#define OTHER_ID_TYPE(X) ((X & OTHER_ID_TYPE_MASK) << OTHER_ID_TYPE_SHIFT)
+#define ID_OPP_NO(X) ((X & OPP_NO_MASK) << OPP_NO_POS)
+#define ID_VDD(X) ((X & VDD_NO_MASK) << VDD_NO_POS)
+#define OMAP(X) ((X >> OMAP_TYPE_SHIFT) & OMAP_TYPE_MASK)
+#define get_opp_no(X) ((X >> OPP_NO_POS) & OPP_NO_MASK)
+#define get_vdd(X) ((X >> VDD_NO_POS) & VDD_NO_MASK)
+
+/* VDD1 OPPs */
+#define PRCM_VDD1_OPP1 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
+ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x1))
+#define PRCM_VDD1_OPP2 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
+ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x2))
+#define PRCM_VDD1_OPP3 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
+ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x3))
+#define PRCM_VDD1_OPP4 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
+ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x4))
+#define PRCM_VDD1_OPP5 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
+ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x5))
+#define PRCM_NO_VDD1_OPPS 5
+
+
+/* VDD2 OPPs */
+#define PRCM_VDD2_OPP1 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
+ ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x1))
+#define PRCM_VDD2_OPP2 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
+ ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x2))
+#define PRCM_VDD2_OPP3 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
+ ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x3))
+#define PRCM_NO_VDD2_OPPS 3
+/* XXX: end remove/move */
+
+
+/* XXX: find more appropriate place for these once DVFS is in place */
extern u32 current_vdd1_opp;
extern u32 current_vdd2_opp;
-extern struct kset power_subsys;

-extern inline int loop_wait(u32 *lcnt, u32 *rcnt, u32 delay);
-extern void omap_udelay(u32 udelay);
+/*
+ * Smartreflex module enable/disable interface.
+ * NOTE: if smartreflex is not enabled from sysfs, these functions will not
+ * do anything.
+ */
+#if defined(CONFIG_ARCH_OMAP34XX) && defined(CONFIG_TWL4030_CORE)
+void enable_smartreflex(int srid);
+void disable_smartreflex(int srid);
+#else
+static inline void enable_smartreflex(int srid) {}
+static inline void disable_smartreflex(int srid) {}
+#endif
+
+
+#endif
+

diff --git a/include/asm-arm/arch-omap/omap34xx.h b/include/asm-arm/arch-omap/omap34xx.h
index 6a0459a..3667fd6 100644
--- a/include/asm-arm/arch-omap/omap34xx.h
+++ b/include/asm-arm/arch-omap/omap34xx.h
@@ -54,6 +54,8 @@
#define OMAP34XX_HSUSB_HOST_BASE (L4_34XX_BASE + 0x64000)
#define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000)
#define IRQ_SIR_IRQ 0x0040
+#define OMAP34XX_SR1_BASE 0x480C9000
+#define OMAP34XX_SR2_BASE 0x480CB000


#if defined(CONFIG_ARCH_OMAP3430)
--
1.5.4.3

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Kalle Jokiniemi
2008-06-02 11:30:12 UTC
Permalink
The following patch set integrates TI's SmartReflex driver. SmartReflex is a
module that adjusts OMAP3 VDD1 and VDD2 operating voltages around the nominal
values of current operating point depending on silicon characteristics and
operating conditions.

The driver creates two sysfs entries into /sys/power/ named "sr_vdd1_autocomp"
and "sr_vdd2_autocomp" which can be used to activate SmartReflex modules 1 and
2.

Use the following commands to enable SmartReflex:

echo -n 1 > /sys/power/sr_vdd1_autocomp
echo -n 1 > /sys/power/sr_vdd2_autocomp

To disable:

echo -n 0 > /sys/power/sr_vdd1_autocomp
echo -n 0 > /sys/power/sr_vdd2_autocomp

This particular patch adds the TI reference source and header files for
SmartReflex. Only modifications include minor styling to pass checkpatch.pl
test.

Signed-off-by: Kalle Jokiniemi <ext-***@nokia.com>
---
arch/arm/mach-omap2/smartreflex.c | 815 +++++++++++++++++++++++++++++++++++++
arch/arm/mach-omap2/smartreflex.h | 136 ++++++
2 files changed, 951 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/smartreflex.c
create mode 100644 arch/arm/mach-omap2/smartreflex.h

diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
new file mode 100644
index 0000000..dae7460
--- /dev/null
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -0,0 +1,815 @@
+/*
+ * linux/arch/arm/mach-omap3/smartreflex.c
+ *
+ * OMAP34XX SmartReflex Voltage Control
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Lesly A M <***@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/sysfs.h>
+
+#include <asm/arch/prcm.h>
+#include <asm/arch/power_companion.h>
+#include <linux/io.h>
+
+#include "prcm-regs.h"
+#include "smartreflex.h"
+
+
+/* #define DEBUG_SR 1 */
+#ifdef DEBUG_SR
+# define DPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__ ,\
+ ## args)
+#else
+# define DPRINTK(fmt, args...)
+#endif
+
+struct omap_sr{
+ int srid;
+ int is_sr_reset;
+ int is_autocomp_active;
+ struct clk *fck;
+ u32 req_opp_no;
+ u32 opp1_nvalue, opp2_nvalue, opp3_nvalue, opp4_nvalue, opp5_nvalue;
+ u32 senp_mod, senn_mod;
+ u32 srbase_addr;
+ u32 vpbase_addr;
+};
+
+static struct omap_sr sr1 = {
+ .srid = SR1,
+ .is_sr_reset = 1,
+ .is_autocomp_active = 0,
+ .srbase_addr = OMAP34XX_SR1_BASE,
+};
+
+static struct omap_sr sr2 = {
+ .srid = SR2,
+ .is_sr_reset = 1,
+ .is_autocomp_active = 0,
+ .srbase_addr = OMAP34XX_SR2_BASE,
+};
+
+static inline void sr_write_reg(struct omap_sr *sr, int offset, u32 value)
+{
+ omap_writel(value, sr->srbase_addr + offset);
+}
+
+static inline void sr_modify_reg(struct omap_sr *sr, int offset, u32 mask,
+ u32 value)
+{
+ u32 reg_val;
+
+ reg_val = omap_readl(sr->srbase_addr + offset);
+ reg_val &= ~mask;
+ reg_val |= value;
+
+ omap_writel(reg_val, sr->srbase_addr + offset);
+}
+
+static inline u32 sr_read_reg(struct omap_sr *sr, int offset)
+{
+ return omap_readl(sr->srbase_addr + offset);
+}
+
+
+#ifndef USE_EFUSE_VALUES
+static void cal_reciprocal(u32 sensor, u32 *sengain, u32 *rnsen)
+{
+ u32 gn, rn, mul;
+
+ for (gn = 0; gn < GAIN_MAXLIMIT; gn++) {
+ mul = 1 << (gn + 8);
+ rn = mul / sensor;
+ if (rn < R_MAXLIMIT) {
+ *sengain = gn;
+ *rnsen = rn;
+ }
+ }
+}
+#endif
+
+static int sr_clk_enable(struct omap_sr *sr)
+{
+ if (clk_enable(sr->fck) != 0) {
+ printk(KERN_ERR "Could not enable sr%d_fck\n", sr->srid);
+ goto clk_enable_err;
+ }
+
+ /* set fclk- active , iclk- idle */
+ sr_modify_reg(sr, ERRCONFIG, SR_CLKACTIVITY_MASK,
+ SR_CLKACTIVITY_IOFF_FON);
+
+ return 0;
+
+clk_enable_err:
+ return -1;
+}
+
+static int sr_clk_disable(struct omap_sr *sr)
+{
+ /* set fclk, iclk- idle */
+ sr_modify_reg(sr, ERRCONFIG, SR_CLKACTIVITY_MASK,
+ SR_CLKACTIVITY_IOFF_FOFF);
+
+ clk_disable(sr->fck);
+ sr->is_sr_reset = 1;
+
+ return 0;
+}
+
+static void sr_set_nvalues(struct omap_sr *sr)
+{
+#ifdef USE_EFUSE_VALUES
+ u32 n1, n2;
+#else
+ u32 senpval, sennval;
+ u32 senpgain, senngain;
+ u32 rnsenp, rnsenn;
+#endif
+
+ if (sr->srid == SR1) {
+#ifdef USE_EFUSE_VALUES
+ /* Read values for VDD1 from EFUSE */
+#else
+ /* since E-Fuse Values are not available, calculating the
+ * reciprocal of the SenN and SenP values for SR1
+ */
+ sr->senp_mod = 0x03; /* SenN-M5 enabled */
+ sr->senn_mod = 0x03;
+
+ /* for OPP5 */
+ senpval = 0x848 + 0x330;
+ sennval = 0xacd + 0x330;
+
+ cal_reciprocal(senpval, &senpgain, &rnsenp);
+ cal_reciprocal(sennval, &senngain, &rnsenn);
+
+ sr->opp5_nvalue =
+ ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
+ (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
+ (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
+ (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
+
+ /* for OPP4 */
+ senpval = 0x727 + 0x2a0;
+ sennval = 0x964 + 0x2a0;
+
+ cal_reciprocal(senpval, &senpgain, &rnsenp);
+ cal_reciprocal(sennval, &senngain, &rnsenn);
+
+ sr->opp4_nvalue =
+ ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
+ (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
+ (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
+ (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
+
+ /* for OPP3 */
+ senpval = 0x655 + 0x200;
+ sennval = 0x85b + 0x200;
+
+ cal_reciprocal(senpval, &senpgain, &rnsenp);
+ cal_reciprocal(sennval, &senngain, &rnsenn);
+
+ sr->opp3_nvalue =
+ ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
+ (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
+ (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
+ (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
+
+ /* for OPP2 */
+ senpval = 0x3be + 0x1a0;
+ sennval = 0x506 + 0x1a0;
+
+ cal_reciprocal(senpval, &senpgain, &rnsenp);
+ cal_reciprocal(sennval, &senngain, &rnsenn);
+
+ sr->opp2_nvalue =
+ ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
+ (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
+ (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
+ (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
+
+ /* for OPP1 */
+ senpval = 0x28c + 0x100;
+ sennval = 0x373 + 0x100;
+
+ cal_reciprocal(senpval, &senpgain, &rnsenp);
+ cal_reciprocal(sennval, &senngain, &rnsenn);
+
+ sr->opp1_nvalue =
+ ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
+ (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
+ (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
+ (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
+
+ sr_clk_enable(sr);
+ sr_write_reg(sr, NVALUERECIPROCAL, sr->opp3_nvalue);
+ sr_clk_disable(sr);
+
+#endif
+ } else if (sr->srid == SR2) {
+#ifdef USE_EFUSE_VALUES
+ /* Read values for VDD2 from EFUSE */
+#else
+ /* since E-Fuse Values are not available, calculating the
+ * reciprocal of the SenN and SenP values for SR2
+ */
+ sr->senp_mod = 0x03;
+ sr->senn_mod = 0x03;
+
+ /* for OPP3 */
+ senpval = 0x579 + 0x200;
+ sennval = 0x76f + 0x200;
+
+ cal_reciprocal(senpval, &senpgain, &rnsenp);
+ cal_reciprocal(sennval, &senngain, &rnsenn);
+
+ sr->opp3_nvalue =
+ ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
+ (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
+ (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
+ (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
+
+ /* for OPP2 */
+ senpval = 0x390 + 0x1c0;
+ sennval = 0x4f5 + 0x1c0;
+
+ cal_reciprocal(senpval, &senpgain, &rnsenp);
+ cal_reciprocal(sennval, &senngain, &rnsenn);
+
+ sr->opp2_nvalue =
+ ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
+ (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
+ (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
+ (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
+
+ /* for OPP1 */
+ senpval = 0x25d;
+ sennval = 0x359;
+
+ cal_reciprocal(senpval, &senpgain, &rnsenp);
+ cal_reciprocal(sennval, &senngain, &rnsenn);
+
+ sr->opp1_nvalue =
+ ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
+ (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
+ (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
+ (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
+
+#endif
+ }
+
+}
+
+static void sr_configure_vp(int srid)
+{
+ u32 vpconfig;
+
+ if (srid == SR1) {
+ vpconfig = PRM_VP1_CONFIG_ERROROFFSET | PRM_VP1_CONFIG_ERRORGAIN
+ | PRM_VP1_CONFIG_INITVOLTAGE | PRM_VP1_CONFIG_TIMEOUTEN;
+
+ PRM_VP1_CONFIG = vpconfig;
+ PRM_VP1_VSTEPMIN = PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN |
+ PRM_VP1_VSTEPMIN_VSTEPMIN;
+
+ PRM_VP1_VSTEPMAX = PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX |
+ PRM_VP1_VSTEPMAX_VSTEPMAX;
+
+ PRM_VP1_VLIMITTO = PRM_VP1_VLIMITTO_VDDMAX |
+ PRM_VP1_VLIMITTO_VDDMIN | PRM_VP1_VLIMITTO_TIMEOUT;
+
+ PRM_VP1_CONFIG |= PRM_VP1_CONFIG_INITVDD;
+ PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_INITVDD;
+
+ } else if (srid == SR2) {
+ vpconfig = PRM_VP2_CONFIG_ERROROFFSET | PRM_VP2_CONFIG_ERRORGAIN
+ | PRM_VP2_CONFIG_INITVOLTAGE | PRM_VP2_CONFIG_TIMEOUTEN;
+
+ PRM_VP2_CONFIG = vpconfig;
+ PRM_VP2_VSTEPMIN = PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN |
+ PRM_VP2_VSTEPMIN_VSTEPMIN;
+
+ PRM_VP2_VSTEPMAX = PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX |
+ PRM_VP2_VSTEPMAX_VSTEPMAX;
+
+ PRM_VP2_VLIMITTO = PRM_VP2_VLIMITTO_VDDMAX |
+ PRM_VP2_VLIMITTO_VDDMIN | PRM_VP2_VLIMITTO_TIMEOUT;
+
+ PRM_VP2_CONFIG |= PRM_VP2_CONFIG_INITVDD;
+ PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_INITVDD;
+
+ }
+}
+
+static void sr_configure_vc(void)
+{
+ PRM_VC_SMPS_SA =
+ (R_SRI2C_SLAVE_ADDR << PRM_VC_SMPS_SA1_SHIFT) |
+ (R_SRI2C_SLAVE_ADDR << PRM_VC_SMPS_SA0_SHIFT);
+
+ PRM_VC_SMPS_VOL_RA = (R_VDD2_SR_CONTROL << PRM_VC_SMPS_VOLRA1_SHIFT) |
+ (R_VDD1_SR_CONTROL << PRM_VC_SMPS_VOLRA0_SHIFT);
+
+ PRM_VC_CMD_VAL_0 = (PRM_VC_CMD_VAL0_ON << PRM_VC_CMD_ON_SHIFT) |
+ (PRM_VC_CMD_VAL0_ONLP << PRM_VC_CMD_ONLP_SHIFT) |
+ (PRM_VC_CMD_VAL0_RET << PRM_VC_CMD_RET_SHIFT) |
+ (PRM_VC_CMD_VAL0_OFF << PRM_VC_CMD_OFF_SHIFT);
+
+ PRM_VC_CMD_VAL_1 = (PRM_VC_CMD_VAL1_ON << PRM_VC_CMD_ON_SHIFT) |
+ (PRM_VC_CMD_VAL1_ONLP << PRM_VC_CMD_ONLP_SHIFT) |
+ (PRM_VC_CMD_VAL1_RET << PRM_VC_CMD_RET_SHIFT) |
+ (PRM_VC_CMD_VAL1_OFF << PRM_VC_CMD_OFF_SHIFT);
+
+ PRM_VC_CH_CONF = PRM_VC_CH_CONF_CMD1 | PRM_VC_CH_CONF_RAV1;
+
+ PRM_VC_I2C_CFG = PRM_VC_I2C_CFG_MCODE | PRM_VC_I2C_CFG_HSEN
+ | PRM_VC_I2C_CFG_SREN;
+
+ /* Setup voltctrl and other setup times */
+#ifdef CONFIG_SYSOFFMODE
+ PRM_VOLTCTRL = PRM_VOLTCTRL_AUTO_OFF | PRM_VOLTCTRL_AUTO_RET;
+ PRM_CLKSETUP = PRM_CLKSETUP_DURATION;
+ PRM_VOLTSETUP1 = (PRM_VOLTSETUP_TIME2 << PRM_VOLTSETUP_TIME2_OFFSET) |
+ (PRM_VOLTSETUP_TIME1 << PRM_VOLTSETUP_TIME1_OFFSET);
+ PRM_VOLTOFFSET = PRM_VOLTOFFSET_DURATION;
+ PRM_VOLTSETUP2 = PRM_VOLTSETUP2_DURATION;
+#else
+ PRM_VOLTCTRL |= PRM_VOLTCTRL_AUTO_RET;
+#endif
+
+}
+
+
+static void sr_configure(struct omap_sr *sr)
+{
+ u32 sys_clk, sr_clk_length = 0;
+ u32 sr_config;
+ u32 senp_en , senn_en;
+
+ senp_en = sr->senp_mod;
+ senn_en = sr->senn_mod;
+
+ sys_clk = prcm_get_system_clock_speed();
+
+ switch (sys_clk) {
+ case 12000:
+ sr_clk_length = SRCLKLENGTH_12MHZ_SYSCLK;
+ break;
+ case 13000:
+ sr_clk_length = SRCLKLENGTH_13MHZ_SYSCLK;
+ break;
+ case 19200:
+ sr_clk_length = SRCLKLENGTH_19MHZ_SYSCLK;
+ break;
+ case 26000:
+ sr_clk_length = SRCLKLENGTH_26MHZ_SYSCLK;
+ break;
+ case 38400:
+ sr_clk_length = SRCLKLENGTH_38MHZ_SYSCLK;
+ break;
+ default :
+ printk(KERN_ERR "Invalid sysclk value\n");
+ break;
+ }
+
+ DPRINTK(KERN_DEBUG "SR : sys clk %lu\n", sys_clk);
+ if (sr->srid == SR1) {
+ sr_config = SR1_SRCONFIG_ACCUMDATA |
+ (sr_clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
+ SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN |
+ SRCONFIG_MINMAXAVG_EN |
+ (senn_en << SRCONFIG_SENNENABLE_SHIFT) |
+ (senp_en << SRCONFIG_SENPENABLE_SHIFT) |
+ SRCONFIG_DELAYCTRL;
+
+ sr_write_reg(sr, SRCONFIG, sr_config);
+
+ sr_write_reg(sr, AVGWEIGHT, SR1_AVGWEIGHT_SENPAVGWEIGHT |
+ SR1_AVGWEIGHT_SENNAVGWEIGHT);
+
+ sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK |
+ SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
+ (SR1_ERRWEIGHT | SR1_ERRMAXLIMIT | SR1_ERRMINLIMIT));
+
+ } else if (sr->srid == SR2) {
+ sr_config = SR2_SRCONFIG_ACCUMDATA |
+ (sr_clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
+ SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN |
+ SRCONFIG_MINMAXAVG_EN |
+ (senn_en << SRCONFIG_SENNENABLE_SHIFT) |
+ (senp_en << SRCONFIG_SENPENABLE_SHIFT) |
+ SRCONFIG_DELAYCTRL;
+
+ sr_write_reg(sr, SRCONFIG, sr_config);
+
+ sr_write_reg(sr, AVGWEIGHT, SR2_AVGWEIGHT_SENPAVGWEIGHT |
+ SR2_AVGWEIGHT_SENNAVGWEIGHT);
+
+ sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK |
+ SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
+ (SR2_ERRWEIGHT | SR2_ERRMAXLIMIT | SR2_ERRMINLIMIT));
+
+ }
+ sr->is_sr_reset = 0;
+}
+
+static void sr_enable(struct omap_sr *sr, u32 target_opp_no)
+{
+ u32 nvalue_reciprocal, current_nvalue;
+
+ sr->req_opp_no = target_opp_no;
+
+ if (sr->srid == SR1) {
+ switch (target_opp_no) {
+ case 5:
+ nvalue_reciprocal = sr->opp5_nvalue;
+ break;
+ case 4:
+ nvalue_reciprocal = sr->opp4_nvalue;
+ break;
+ case 3:
+ nvalue_reciprocal = sr->opp3_nvalue;
+ break;
+ case 2:
+ nvalue_reciprocal = sr->opp2_nvalue;
+ break;
+ case 1:
+ nvalue_reciprocal = sr->opp1_nvalue;
+ break;
+ default:
+ nvalue_reciprocal = sr->opp3_nvalue;
+ break;
+ }
+ } else {
+ switch (target_opp_no) {
+ case 3:
+ nvalue_reciprocal = sr->opp3_nvalue;
+ break;
+ case 2:
+ nvalue_reciprocal = sr->opp2_nvalue;
+ break;
+ case 1:
+ nvalue_reciprocal = sr->opp1_nvalue;
+ break;
+ default:
+ nvalue_reciprocal = sr->opp3_nvalue;
+ break;
+ }
+ }
+
+ current_nvalue = sr_read_reg(sr, NVALUERECIPROCAL);
+
+ if (current_nvalue == nvalue_reciprocal) {
+ DPRINTK("System is already at the desired voltage level\n");
+ return;
+ }
+
+ sr_write_reg(sr, NVALUERECIPROCAL, nvalue_reciprocal);
+
+ /* Enable the interrupt */
+ sr_modify_reg(sr, ERRCONFIG,
+ (ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST),
+ (ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST));
+
+ if (sr->srid == SR1) {
+ /* Enable VP1 */
+ PRM_VP1_CONFIG |= PRM_VP1_CONFIG_VPENABLE;
+ } else if (sr->srid == SR2) {
+ /* Enable VP2 */
+ PRM_VP2_CONFIG |= PRM_VP2_CONFIG_VPENABLE;
+ }
+
+ /* SRCONFIG - enable SR */
+ sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE);
+
+}
+
+static void sr_disable(struct omap_sr *sr)
+{
+ sr->is_sr_reset = 1;
+
+ /* SRCONFIG - disable SR */
+ sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, ~SRCONFIG_SRENABLE);
+
+ if (sr->srid == SR1) {
+ /* Enable VP1 */
+ PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_VPENABLE;
+ } else if (sr->srid == SR2) {
+ /* Enable VP2 */
+ PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_VPENABLE;
+ }
+}
+
+
+void sr_start_vddautocomap(int srid, u32 target_opp_no)
+{
+ struct omap_sr *sr = NULL;
+
+ if (srid == SR1)
+ sr = &sr1;
+ else if (srid == SR2)
+ sr = &sr2;
+
+ if (sr->is_sr_reset == 1) {
+ sr_clk_enable(sr);
+ sr_configure(sr);
+ }
+
+ if (sr->is_autocomp_active == 1)
+ DPRINTK(KERN_WARNING "SR%d: VDD autocomp is already active\n",
+ srid);
+
+ sr->is_autocomp_active = 1;
+ sr_enable(sr, target_opp_no);
+}
+EXPORT_SYMBOL(sr_start_vddautocomap);
+
+int sr_stop_vddautocomap(int srid)
+{
+ struct omap_sr *sr = NULL;
+
+ if (srid == SR1)
+ sr = &sr1;
+ else if (srid == SR2)
+ sr = &sr2;
+
+ if (sr->is_autocomp_active == 1) {
+ sr_disable(sr);
+ sr_clk_disable(sr);
+ sr->is_autocomp_active = 0;
+ return SR_TRUE;
+ } else {
+ DPRINTK(KERN_WARNING "SR%d: VDD autocomp is not active\n",
+ srid);
+ return SR_FALSE;
+ }
+
+}
+EXPORT_SYMBOL(sr_stop_vddautocomap);
+
+void enable_smartreflex(int srid)
+{
+ u32 target_opp_no = 0;
+ struct omap_sr *sr = NULL;
+
+ if (srid == SR1)
+ sr = &sr1;
+ else if (srid == SR2)
+ sr = &sr2;
+
+ if (sr->is_autocomp_active == 1) {
+ if (sr->is_sr_reset == 1) {
+ if (srid == SR1) {
+ /* Enable SR clks */
+ CM_FCLKEN_WKUP |= SR1_CLK_ENABLE;
+ target_opp_no = get_opp_no(current_vdd1_opp);
+
+ } else if (srid == SR2) {
+ /* Enable SR clks */
+ CM_FCLKEN_WKUP |= SR2_CLK_ENABLE;
+ target_opp_no = get_opp_no(current_vdd2_opp);
+ }
+
+ sr_configure(sr);
+
+ sr_enable(sr, target_opp_no);
+ }
+ }
+}
+
+void disable_smartreflex(int srid)
+{
+ struct omap_sr *sr = NULL;
+
+ if (srid == SR1)
+ sr = &sr1;
+ else if (srid == SR2)
+ sr = &sr2;
+
+ if (sr->is_autocomp_active == 1) {
+ if (srid == SR1) {
+ /* Enable SR clk */
+ CM_FCLKEN_WKUP |= SR1_CLK_ENABLE;
+
+ } else if (srid == SR2) {
+ /* Enable SR clk */
+ CM_FCLKEN_WKUP |= SR2_CLK_ENABLE;
+ }
+
+ if (sr->is_sr_reset == 0) {
+
+ sr->is_sr_reset = 1;
+ /* SRCONFIG - disable SR */
+ sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE,
+ ~SRCONFIG_SRENABLE);
+
+ if (sr->srid == SR1) {
+ /* Disable SR clk */
+ CM_FCLKEN_WKUP &= ~SR1_CLK_ENABLE;
+ /* Enable VP1 */
+ PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_VPENABLE;
+
+ } else if (sr->srid == SR2) {
+ /* Disable SR clk */
+ CM_FCLKEN_WKUP &= ~SR2_CLK_ENABLE;
+ /* Enable VP2 */
+ PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_VPENABLE;
+ }
+ }
+ }
+}
+
+
+/* Voltage Scaling using SR VCBYPASS */
+int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel)
+{
+ int ret;
+ int sr_status = 0;
+ u32 vdd, target_opp_no;
+ u32 vc_bypass_value;
+ u32 reg_addr = 0;
+ u32 loop_cnt = 0, retries_cnt = 0;
+
+ vdd = get_vdd(target_opp);
+ target_opp_no = get_opp_no(target_opp);
+
+ if (vdd == PRCM_VDD1) {
+ sr_status = sr_stop_vddautocomap(SR1);
+
+ PRM_VC_CMD_VAL_0 = (PRM_VC_CMD_VAL_0 & ~PRM_VC_CMD_ON_MASK) |
+ (vsel << PRM_VC_CMD_ON_SHIFT);
+ reg_addr = R_VDD1_SR_CONTROL;
+
+ } else if (vdd == PRCM_VDD2) {
+ sr_status = sr_stop_vddautocomap(SR2);
+
+ PRM_VC_CMD_VAL_1 = (PRM_VC_CMD_VAL_1 & ~PRM_VC_CMD_ON_MASK) |
+ (vsel << PRM_VC_CMD_ON_SHIFT);
+ reg_addr = R_VDD2_SR_CONTROL;
+ }
+
+ vc_bypass_value = (vsel << PRM_VC_BYPASS_DATA_SHIFT) |
+ (reg_addr << PRM_VC_BYPASS_REGADDR_SHIFT) |
+ (R_SRI2C_SLAVE_ADDR << PRM_VC_BYPASS_SLAVEADDR_SHIFT);
+
+ PRM_VC_BYPASS_VAL = vc_bypass_value;
+
+ PRM_VC_BYPASS_VAL |= PRM_VC_BYPASS_VALID;
+
+ DPRINTK("%s : PRM_VC_BYPASS_VAL %X\n", __func__, PRM_VC_BYPASS_VAL);
+ DPRINTK("PRM_IRQST_MPU %X\n", PRM_IRQSTATUS_MPU);
+
+ while ((PRM_VC_BYPASS_VAL & PRM_VC_BYPASS_VALID) != 0x0) {
+ ret = loop_wait(&loop_cnt, &retries_cnt, 10);
+ if (ret != PRCM_PASS) {
+ printk(KERN_INFO "Loop count exceeded in check SR I2C"
+ "write\n");
+ return ret;
+ }
+ }
+
+ omap_udelay(T2_SMPS_UPDATE_DELAY);
+
+ if (sr_status) {
+ if (vdd == PRCM_VDD1)
+ sr_start_vddautocomap(SR1, target_opp_no);
+ else if (vdd == PRCM_VDD2)
+ sr_start_vddautocomap(SR2, target_opp_no);
+ }
+
+ return SR_PASS;
+}
+
+/* Sysfs interface to select SR VDD1 auto compensation */
+static ssize_t omap_sr_vdd1_autocomp_show(struct kset *subsys, char *buf)
+{
+ return sprintf(buf, "%d\n", sr1.is_autocomp_active);
+}
+
+static ssize_t omap_sr_vdd1_autocomp_store(struct kset *subsys,
+ const char *buf, size_t n)
+{
+ u32 current_vdd1opp_no;
+ unsigned short value;
+
+ if (sscanf(buf, "%hu", &value) != 1 || (value > 1)) {
+ printk(KERN_ERR "sr_vdd1_autocomp: Invalid value\n");
+ return -EINVAL;
+ }
+
+ current_vdd1opp_no = get_opp_no(current_vdd1_opp);
+
+ if (value == 0)
+ sr_stop_vddautocomap(SR1);
+ else
+ sr_start_vddautocomap(SR1, current_vdd1opp_no);
+
+ return n;
+}
+
+static struct subsys_attribute sr_vdd1_autocomp = {
+ .attr = {
+ .name = __stringify(sr_vdd1_autocomp),
+ .mode = 0644,
+ },
+ .show = omap_sr_vdd1_autocomp_show,
+ .store = omap_sr_vdd1_autocomp_store,
+};
+
+/* Sysfs interface to select SR VDD2 auto compensation */
+static ssize_t omap_sr_vdd2_autocomp_show(struct kset *subsys, char *buf)
+{
+ return sprintf(buf, "%d\n", sr2.is_autocomp_active);
+}
+
+static ssize_t omap_sr_vdd2_autocomp_store(struct kset *subsys,
+ const char *buf, size_t n)
+{
+ u32 current_vdd2opp_no;
+ unsigned short value;
+
+ if (sscanf(buf, "%hu", &value) != 1 || (value > 1)) {
+ printk(KERN_ERR "sr_vdd2_autocomp: Invalid value\n");
+ return -EINVAL;
+ }
+
+ current_vdd2opp_no = get_opp_no(current_vdd2_opp);
+
+ if (value == 0)
+ sr_stop_vddautocomap(SR2);
+ else
+ sr_start_vddautocomap(SR2, current_vdd2opp_no);
+
+ return n;
+}
+
+static struct subsys_attribute sr_vdd2_autocomp = {
+ .attr = {
+ .name = __stringify(sr_vdd2_autocomp),
+ .mode = 0644,
+ },
+ .show = omap_sr_vdd2_autocomp_show,
+ .store = omap_sr_vdd2_autocomp_store,
+};
+
+
+
+static int __init omap3_sr_init(void)
+{
+ int ret = 0;
+ u8 RdReg;
+
+#ifdef CONFIG_ARCH_OMAP34XX
+ sr1.fck = clk_get(NULL, "sr1_fck");
+ if (IS_ERR(sr1.fck))
+ printk(KERN_ERR "Could not get sr1_fck\n");
+
+ sr2.fck = clk_get(NULL, "sr2_fck");
+ if (IS_ERR(sr2.fck))
+ printk(KERN_ERR "Could not get sr2_fck\n");
+#endif /* #ifdef CONFIG_ARCH_OMAP34XX */
+
+ /* Call the VPConfig, VCConfig, set N Values. */
+ sr_set_nvalues(&sr1);
+ sr_configure_vp(SR1);
+
+ sr_set_nvalues(&sr2);
+ sr_configure_vp(SR2);
+
+ sr_configure_vc();
+
+ /* Enable SR on T2 */
+ ret = t2_in(PM_RECEIVER, &RdReg, R_DCDC_GLOBAL_CFG);
+ RdReg |= DCDC_GLOBAL_CFG_ENABLE_SRFLX;
+ ret |= t2_out(PM_RECEIVER, RdReg, R_DCDC_GLOBAL_CFG);
+
+
+ printk(KERN_INFO "SmartReflex driver initialized\n");
+
+ ret = subsys_create_file(&power_subsys, &sr_vdd1_autocomp);
+ if (ret)
+ printk(KERN_ERR "subsys_create_file failed: %d\n", ret);
+
+ ret = subsys_create_file(&power_subsys, &sr_vdd2_autocomp);
+ if (ret)
+ printk(KERN_ERR "subsys_create_file failed: %d\n", ret);
+
+ return 0;
+}
+
+arch_initcall(omap3_sr_init);
diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
new file mode 100644
index 0000000..62907ef
--- /dev/null
+++ b/arch/arm/mach-omap2/smartreflex.h
@@ -0,0 +1,136 @@
+/*
+ * linux/arch/arm/mach-omap3/smartreflex.h
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Lesly A M <***@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+
+/* SR Modules */
+#define SR1 1
+#define SR2 2
+
+#define SR_FAIL 1
+#define SR_PASS 0
+
+#define SR_TRUE 1
+#define SR_FALSE 0
+
+#define GAIN_MAXLIMIT 16
+#define R_MAXLIMIT 256
+
+#define SR1_CLK_ENABLE (0x1 << 6)
+#define SR2_CLK_ENABLE (0x1 << 7)
+
+/* PRM_VP1_CONFIG */
+#define PRM_VP1_CONFIG_ERROROFFSET (0x00 << 24)
+#define PRM_VP1_CONFIG_ERRORGAIN (0x20 << 16)
+
+#define PRM_VP1_CONFIG_INITVOLTAGE (0x30 << 8) /* 1.2 volt */
+#define PRM_VP1_CONFIG_TIMEOUTEN (0x1 << 3)
+#define PRM_VP1_CONFIG_INITVDD (0x1 << 2)
+#define PRM_VP1_CONFIG_FORCEUPDATE (0x1 << 1)
+#define PRM_VP1_CONFIG_VPENABLE (0x1 << 0)
+
+/* PRM_VP1_VSTEPMIN */
+#define PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN (0x01F4 << 8)
+#define PRM_VP1_VSTEPMIN_VSTEPMIN (0x01 << 0)
+
+/* PRM_VP1_VSTEPMAX */
+#define PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX (0x01F4 << 8)
+#define PRM_VP1_VSTEPMAX_VSTEPMAX (0x04 << 0)
+
+/* PRM_VP1_VLIMITTO */
+#define PRM_VP1_VLIMITTO_VDDMAX (0x3C << 24)
+#define PRM_VP1_VLIMITTO_VDDMIN (0x0 << 16)
+#define PRM_VP1_VLIMITTO_TIMEOUT (0xFFFF << 0)
+
+/* PRM_VP2_CONFIG */
+#define PRM_VP2_CONFIG_ERROROFFSET (0x00 << 24)
+#define PRM_VP2_CONFIG_ERRORGAIN (0x20 << 16)
+
+#define PRM_VP2_CONFIG_INITVOLTAGE (0x30 << 8) /* 1.2 volt */
+#define PRM_VP2_CONFIG_TIMEOUTEN (0x1 << 3)
+#define PRM_VP2_CONFIG_INITVDD (0x1 << 2)
+#define PRM_VP2_CONFIG_FORCEUPDATE (0x1 << 1)
+#define PRM_VP2_CONFIG_VPENABLE (0x1 << 0)
+
+/* PRM_VP2_VSTEPMIN */
+#define PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN (0x01F4 << 8)
+#define PRM_VP2_VSTEPMIN_VSTEPMIN (0x01 << 0)
+
+/* PRM_VP2_VSTEPMAX */
+#define PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX (0x01F4 << 8)
+#define PRM_VP2_VSTEPMAX_VSTEPMAX (0x04 << 0)
+
+/* PRM_VP2_VLIMITTO */
+#define PRM_VP2_VLIMITTO_VDDMAX (0x2C << 24)
+#define PRM_VP2_VLIMITTO_VDDMIN (0x0 << 16)
+#define PRM_VP2_VLIMITTO_TIMEOUT (0xFFFF << 0)
+
+/* SRCONFIG */
+#define SR1_SRCONFIG_ACCUMDATA (0x1F4 << 22)
+#define SR2_SRCONFIG_ACCUMDATA (0x1F4 << 22)
+
+#define SRCLKLENGTH_12MHZ_SYSCLK 0x3C
+#define SRCLKLENGTH_13MHZ_SYSCLK 0x41
+#define SRCLKLENGTH_19MHZ_SYSCLK 0x60
+#define SRCLKLENGTH_26MHZ_SYSCLK 0x82
+#define SRCLKLENGTH_38MHZ_SYSCLK 0xC0
+
+#define SRCONFIG_SRCLKLENGTH_SHIFT 12
+#define SRCONFIG_SENNENABLE_SHIFT 5
+#define SRCONFIG_SENPENABLE_SHIFT 3
+
+#define SRCONFIG_SRENABLE (0x01 << 11)
+#define SRCONFIG_SENENABLE (0x01 << 10)
+#define SRCONFIG_ERRGEN_EN (0x01 << 9)
+#define SRCONFIG_MINMAXAVG_EN (0x01 << 8)
+
+#define SRCONFIG_DELAYCTRL (0x01 << 2)
+#define SRCONFIG_CLKCTRL (0x00 << 0)
+
+/* AVGWEIGHT */
+#define SR1_AVGWEIGHT_SENPAVGWEIGHT (0x03 << 2)
+#define SR1_AVGWEIGHT_SENNAVGWEIGHT (0x03 << 0)
+
+#define SR2_AVGWEIGHT_SENPAVGWEIGHT (0x01 << 2)
+#define SR2_AVGWEIGHT_SENNAVGWEIGHT (0x01 << 0)
+
+/* NVALUERECIPROCAL */
+#define NVALUERECIPROCAL_SENPGAIN_SHIFT 20
+#define NVALUERECIPROCAL_SENNGAIN_SHIFT 16
+#define NVALUERECIPROCAL_RNSENP_SHIFT 8
+#define NVALUERECIPROCAL_RNSENN_SHIFT 0
+
+/* ERRCONFIG */
+#define SR_CLKACTIVITY_MASK (0x03 << 20)
+#define SR_ERRWEIGHT_MASK (0x07 << 16)
+#define SR_ERRMAXLIMIT_MASK (0xFF << 8)
+#define SR_ERRMINLIMIT_MASK (0xFF << 0)
+
+#define SR_CLKACTIVITY_IOFF_FOFF (0x00 << 20)
+#define SR_CLKACTIVITY_IOFF_FON (0x02 << 20)
+
+#define ERRCONFIG_VPBOUNDINTEN (0x1 << 31)
+#define ERRCONFIG_VPBOUNDINTST (0x1 << 30)
+
+#define SR1_ERRWEIGHT (0x07 << 16)
+#define SR1_ERRMAXLIMIT (0x02 << 8)
+#define SR1_ERRMINLIMIT (0xFA << 0)
+
+#define SR2_ERRWEIGHT (0x07 << 16)
+#define SR2_ERRMAXLIMIT (0x02 << 8)
+#define SR2_ERRMINLIMIT (0xF9 << 0)
+
+extern u32 current_vdd1_opp;
+extern u32 current_vdd2_opp;
+extern struct kset power_subsys;
+
+extern inline int loop_wait(u32 *lcnt, u32 *rcnt, u32 delay);
+extern void omap_udelay(u32 udelay);
+
--
1.5.4.3

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Tero Kristo
2008-06-03 10:47:02 UTC
Permalink
UART usage (e.g. serial console) now denies sleep for 5 seconds. This
makes it possible to use serial console when dynamic idle is enabled.

Also moved code from pm-debug.c to serial.c, and made pm24xx.c use this
new implementation.

Signed-off-by: Tero Kristo <***@nokia.com>
---
arch/arm/mach-omap2/pm-debug.c | 132 ------------------------------------
arch/arm/mach-omap2/pm.h | 8 --
arch/arm/mach-omap2/pm24xx.c | 53 ++++++++++-----
arch/arm/mach-omap2/pm34xx.c | 5 ++
arch/arm/mach-omap2/serial.c | 118 ++++++++++++++++++++++++++++++++
include/asm-arm/arch-omap/common.h | 3 +
6 files changed, 162 insertions(+), 157 deletions(-)

diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 8a9f3c4..c20fa3b 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -34,138 +34,6 @@
#ifdef CONFIG_PM_DEBUG
int omap2_pm_debug = 0;

-static int serial_console_clock_disabled;
-static int serial_console_uart;
-static unsigned int serial_console_next_disable;
-
-static struct clk *console_iclk, *console_fclk;
-
-static void serial_console_kick(void)
-{
- serial_console_next_disable = omap2_read_32k_sync_counter();
- /* Keep the clocks on for 4 secs */
- serial_console_next_disable += 4 * 32768;
-}
-
-static void serial_wait_tx(void)
-{
- static const unsigned long uart_bases[3] = {
- 0x4806a000, 0x4806c000, 0x4806e000
- };
- unsigned long lsr_reg;
- int looped = 0;
-
- /* Wait for TX FIFO and THR to get empty */
- lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart - 1] + (5 << 2));
- while ((__raw_readb(lsr_reg) & 0x60) != 0x60)
- looped = 1;
- if (looped)
- serial_console_kick();
-}
-
-u32 omap2_read_32k_sync_counter(void)
-{
- return omap_readl(OMAP2_32KSYNCT_BASE + 0x0010);
-}
-
-void serial_console_fclk_mask(u32 *f1, u32 *f2)
-{
- switch (serial_console_uart) {
- case 1:
- *f1 &= ~(1 << 21);
- break;
- case 2:
- *f1 &= ~(1 << 22);
- break;
- case 3:
- *f2 &= ~(1 << 2);
- break;
- }
-}
-
-void serial_console_sleep(int enable)
-{
- if (console_iclk == NULL || console_fclk == NULL)
- return;
-
- if (enable) {
- BUG_ON(serial_console_clock_disabled);
- if (clk_get_usecount(console_fclk) == 0)
- return;
- if ((int) serial_console_next_disable - (int) omap2_read_32k_sync_counter() >= 0)
- return;
- serial_wait_tx();
- clk_disable(console_iclk);
- clk_disable(console_fclk);
- serial_console_clock_disabled = 1;
- } else {
- int serial_wakeup = 0;
- u32 l;
-
- switch (serial_console_uart) {
- case 1:
- l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
- if (l & OMAP24XX_ST_UART1)
- serial_wakeup = 1;
- break;
- case 2:
- l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
- if (l & OMAP24XX_ST_UART2)
- serial_wakeup = 1;
- break;
- case 3:
- l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKST2);
- if (l & OMAP24XX_ST_UART3)
- serial_wakeup = 1;
- break;
- }
- if (serial_wakeup)
- serial_console_kick();
- if (!serial_console_clock_disabled)
- return;
- clk_enable(console_iclk);
- clk_enable(console_fclk);
- serial_console_clock_disabled = 0;
- }
-}
-
-void pm_init_serial_console(void)
-{
- const struct omap_serial_console_config *conf;
- char name[16];
-
- conf = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
- struct omap_serial_console_config);
- if (conf == NULL)
- return;
- if (conf->console_uart > 3 || conf->console_uart < 1)
- return;
- serial_console_uart = conf->console_uart;
- sprintf(name, "uart%d_fck", conf->console_uart);
- console_fclk = clk_get(NULL, name);
- if (IS_ERR(console_fclk))
- console_fclk = NULL;
- name[6] = 'i';
- console_iclk = clk_get(NULL, name);
- if (IS_ERR(console_fclk))
- console_iclk = NULL;
- if (console_fclk == NULL || console_iclk == NULL) {
- serial_console_uart = 0;
- return;
- }
- switch (serial_console_uart) {
- case 1:
- prm_set_mod_reg_bits(OMAP24XX_ST_UART1, CORE_MOD, PM_WKEN1);
- break;
- case 2:
- prm_set_mod_reg_bits(OMAP24XX_ST_UART2, CORE_MOD, PM_WKEN1);
- break;
- case 3:
- prm_set_mod_reg_bits(OMAP24XX_ST_UART3, CORE_MOD, OMAP24XX_PM_WKEN2);
- break;
- }
-}
-
#define DUMP_PRM_MOD_REG(mod, reg) \
regs[reg_count].name = #mod "." #reg; \
regs[reg_count++].val = prm_read_mod_reg(mod, reg)
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 351456e..a1a35ea 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -20,18 +20,10 @@ extern unsigned short enable_dyn_sleep;
extern atomic_t sleep_block;

#ifdef CONFIG_PM_DEBUG
-extern u32 omap2_read_32k_sync_counter(void);
extern void omap2_pm_dump(int mode, int resume, unsigned int us);
-extern void serial_console_fclk_mask(u32 *f1, u32 *f2);
-extern void pm_init_serial_console(void);
-extern void serial_console_sleep(int enable);
extern int omap2_pm_debug;
#else
-#define omap2_read_32k_sync_counter() 0;
-#define serial_console_sleep(enable) do; while(0)
-#define pm_init_serial_console() do; while(0)
#define omap2_pm_dump(mode,resume,us) do; while(0)
-#define serial_console_fclk_mask(f1,f2) do; while(0)
#define omap2_pm_debug 0
#endif /* CONFIG_PM_DEBUG */
#endif
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index bcf3afe..b65c0bb 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -44,6 +44,7 @@
#include <asm/arch/mux.h>
#include <asm/arch/dma.h>
#include <asm/arch/board.h>
+#include <asm/arch/common.h>

#include "prm.h"
#include "prm-regbits-24xx.h"
@@ -73,7 +74,9 @@ static int omap2_fclks_active(void)

f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
- serial_console_fclk_mask(&f1, &f2);
+#ifdef CONFIG_PM_DEBUG
+ omap_serial_fclk_mask(&f1, &f2);
+#endif
if (f1 | f2)
return 1;
return 0;
@@ -81,7 +84,8 @@ static int omap2_fclks_active(void)

static void omap2_enter_full_retention(void)
{
- u32 l, sleep_time = 0;
+ u32 l = 0;
+ s64 sleep_time = 0;

/* There is 1 reference hold for all children of the oscillator
* clock, the following will remove it. If no one else uses the
@@ -110,29 +114,38 @@ static void omap2_enter_full_retention(void)
omap2_gpio_prepare_for_retention();

if (omap2_pm_debug) {
+ struct timespec t;
omap2_pm_dump(0, 0, 0);
- sleep_time = omap2_read_32k_sync_counter();
+ getnstimeofday(&t);
+ sleep_time = timespec_to_ns(&t);
}

+#ifdef CONFIG_PM_DEBUG
+ omap_serial_enable_clocks(0);
+#endif
+
/* One last check for pending IRQs to avoid extra latency due
* to sleeping unnecessarily. */
if (omap_irq_pending())
goto no_sleep;

- serial_console_sleep(1);
/* Jump to SRAM suspend code */
omap2_sram_suspend(OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
no_sleep:
- serial_console_sleep(0);
+#ifdef CONFIG_PM_DEBUG
+ omap_serial_check_wakeup();
+ omap_serial_enable_clocks(1);
+#endif

if (omap2_pm_debug) {
unsigned long long tmp;
- u32 resume_time;
+ s64 resume_time;
+ struct timespec t;

- resume_time = omap2_read_32k_sync_counter();
+ getnstimeofday(&t);
+ resume_time = timespec_to_ns(&t);
tmp = resume_time - sleep_time;
- tmp *= 1000000;
- omap2_pm_dump(0, 1, tmp / 32768);
+ omap2_pm_dump(0, 1, tmp / 1000);
}
omap2_gpio_resume_after_retention();

@@ -193,7 +206,7 @@ static int omap2_allow_mpu_retention(void)

static void omap2_enter_mpu_retention(void)
{
- u32 sleep_time = 0;
+ s64 sleep_time = 0;
int only_idle = 0;

/* Putting MPU into the WFI state while a transfer is active
@@ -221,20 +234,24 @@ static void omap2_enter_mpu_retention(void)
}

if (omap2_pm_debug) {
+ struct timespec t;
+
omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
- sleep_time = omap2_read_32k_sync_counter();
+ getnstimeofday(&t);
+ sleep_time = timespec_to_ns(&t);
}

omap2_sram_idle();

if (omap2_pm_debug) {
unsigned long long tmp;
- u32 resume_time;
+ s64 resume_time;
+ struct timespec t;

- resume_time = omap2_read_32k_sync_counter();
+ getnstimeofday(&t);
+ resume_time = timespec_to_ns(&t);
tmp = resume_time - sleep_time;
- tmp *= 1000000;
- omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 32768);
+ omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 1000);
}
}

@@ -250,6 +267,10 @@ static int omap2_can_sleep(void)
return 0;
if (omap_dma_running())
return 0;
+#ifdef CONFIG_PM_DEBUG
+ if (!omap_serial_can_sleep())
+ return 0;
+#endif

return 1;
}
@@ -517,8 +538,6 @@ int __init omap2_pm_init(void)

prcm_setup_regs();

- pm_init_serial_console();
-
/* Hack to prevent MPU retention when STI console is enabled. */
{
const struct omap_sti_console_config *sti;
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 7e775cc..b047d47 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -58,6 +58,9 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
u32 wkst, irqstatus_mpu;
u32 fclk, iclk;

+ /* Check if we woke up to serial console activity */
+ omap_serial_check_wakeup();
+
/* WKUP */
wkst = prm_read_mod_reg(WKUP_MOD, PM_WKST);
if (wkst) {
@@ -176,6 +179,8 @@ static int omap3_can_sleep(void)
return 0;
if (atomic_read(&sleep_block) > 0)
return 0;
+ if (!omap_serial_can_sleep())
+ return 0;
return 1;
}

diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index b0fa582..65571f9 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -23,8 +23,47 @@
#include <asm/arch/common.h>
#include <asm/arch/board.h>

+#include "prm.h"
+#include "pm.h"
+
+#define SERIAL_AWAKE_TIME 5
+
static struct clk *uart_ick[OMAP_MAX_NR_PORTS];
static struct clk *uart_fck[OMAP_MAX_NR_PORTS];
+static s64 omap_serial_next_sleep;
+
+static const u32 omap2_uart_wk_st[OMAP_MAX_NR_PORTS] = {
+ PM_WKST1, PM_WKST1, OMAP24XX_PM_WKST2
+};
+static const u32 omap2_uart_wk_en[OMAP_MAX_NR_PORTS] = {
+ PM_WKEN1, PM_WKEN1, OMAP24XX_PM_WKEN2
+};
+const u32 omap2_uart_wk_bit[OMAP_MAX_NR_PORTS] = {
+ OMAP24XX_ST_UART1, OMAP24XX_ST_UART2, OMAP24XX_ST_UART3
+};
+
+#if defined(CONFIG_ARCH_OMAP2)
+static const u32 omap_uart_fclk_mask[OMAP_MAX_NR_PORTS] = {
+ OMAP24XX_EN_UART1, OMAP24XX_EN_UART2, OMAP24XX_EN_UART3
+};
+#endif
+
+#if defined(CONFIG_ARCH_OMAP3)
+static const u32 omap_uart_fclk_mask[OMAP_MAX_NR_PORTS] = {
+ OMAP3430_EN_UART1, OMAP3430_EN_UART2, OMAP3430_EN_UART3
+};
+
+/* UART padconfig registers, these may differ if non-default padconfig
+ is used */
+#define CONTROL_PADCONF_UART1_RX 0x48002182
+#define CONTROL_PADCONF_UART2_RX 0x4800217A
+#define CONTROL_PADCONF_UART3_RX 0x4800219E
+#define PADCONF_WAKEUP_ST 0x8000
+
+static const u32 omap_uart_padconf[OMAP_MAX_NR_PORTS] = {
+ CONTROL_PADCONF_UART1_RX, CONTROL_PADCONF_UART2_RX, CONTROL_PADCONF_UART3_RX
+};
+#endif

static struct plat_serial8250_port serial_platform_data[] = {
{
@@ -83,6 +122,15 @@ static inline void __init omap_serial_reset(struct plat_serial8250_port *p)
serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
}

+static void omap_serial_kick(void)
+{
+ struct timespec t;
+
+ getnstimeofday(&t);
+ omap_serial_next_sleep = timespec_to_ns(&t) +
+ (s64)SERIAL_AWAKE_TIME * (s64)1000000000;
+}
+
void omap_serial_enable_clocks(int enable)
{
int i;
@@ -99,6 +147,71 @@ void omap_serial_enable_clocks(int enable)
}
}

+void omap_serial_fclk_mask(u32 *f1, u32 *f2)
+{
+ if (uart_ick[0])
+ *f1 &= ~omap_uart_fclk_mask[0];
+ if (uart_ick[1])
+ *f1 &= ~omap_uart_fclk_mask[1];
+ if (uart_ick[2])
+ *f2 &= ~omap_uart_fclk_mask[2];
+}
+
+void omap_serial_check_wakeup(void)
+{
+ int i;
+
+ if (cpu_is_omap34xx())
+ for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
+ if (!uart_ick[i])
+ continue;
+ if (omap_readw(omap_uart_padconf[i]) & PADCONF_WAKEUP_ST)
+ omap_serial_kick();
+ return;
+ }
+
+ if (cpu_is_omap24xx()) {
+ u32 l;
+
+ for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
+ if (!uart_ick[i])
+ continue;
+ l = prm_read_mod_reg(CORE_MOD, omap2_uart_wk_st[i]);
+ if (l & omap2_uart_wk_bit[i])
+ omap_serial_kick();
+ return;
+ }
+ }
+}
+
+int omap_serial_can_sleep(void)
+{
+ s64 cnt;
+ int i;
+ struct timespec t;
+
+ struct plat_serial8250_port *p = serial_platform_data;
+
+ getnstimeofday(&t);
+ cnt = timespec_to_ns(&t);
+
+ for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
+ if (!uart_ick[i])
+ continue;
+ /* Check if we have data in the transmit buffer */
+ if ((serial_read_reg(p + i, UART_LSR) & (UART_LSR_TEMT|UART_LSR_THRE))
+ != (UART_LSR_TEMT|UART_LSR_THRE)) {
+ omap_serial_kick();
+ return 0;
+ }
+ }
+
+ if (omap_serial_next_sleep - cnt >= 0)
+ return 0;
+
+ return 1;
+}
+
void __init omap_serial_init(void)
{
int i;
@@ -142,7 +255,12 @@ void __init omap_serial_init(void)
clk_enable(uart_fck[i]);

omap_serial_reset(p);
+
+ if (cpu_is_omap24xx())
+ prm_set_mod_reg_bits(omap2_uart_wk_bit[i], CORE_MOD, omap2_uart_wk_en[i]);
}
+
+ omap_serial_kick();
}

static struct platform_device serial_device = {
diff --git a/include/asm-arm/arch-omap/common.h b/include/asm-arm/arch-omap/common.h
index 7a48fc9..5d2033b 100644
--- a/include/asm-arm/arch-omap/common.h
+++ b/include/asm-arm/arch-omap/common.h
@@ -35,6 +35,9 @@ extern void omap_map_common_io(void);
extern struct sys_timer omap_timer;
extern void omap_serial_init(void);
extern void omap_serial_enable_clocks(int enable);
+extern int omap_serial_can_sleep(void);
+extern void omap_serial_fclk_mask(u32 *f1, u32 *f2);
+void omap_serial_check_wakeup(void);
#ifdef CONFIG_I2C_OMAP
extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
struct i2c_board_info const *info,
--
1.5.4.3

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Tero Kristo
2008-06-03 10:50:41 UTC
Permalink
This patch depends on the PM patch set sent by Jouni Hogander. Basically just a cosmetic modification to make fclk mask look more nice inside pm34xx.c.


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Tero Kristo
2008-06-03 10:50:42 UTC
Permalink
Signed-off-by: Tero Kristo <***@nokia.com>
---
arch/arm/mach-omap2/pm34xx.c | 3 +--
1 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index ada87ba..2574586 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -245,8 +245,7 @@ static int omap3_fclks_active(void)
fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
CM_FCLKEN);
gpio_fclk_mask(&fck_per);
- fck_core1 &= ~(0x3 << 13);
- fck_per &= ~(0x1 << 11);
+ omap_serial_fclk_mask(&fck_core1, &fck_per);
if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
fck_cam | fck_per | fck_usbhost)
return 1;
--
1.5.4.3

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